Add Support for Xilinx KCU116 (#322)

* initial kcu116 support

* add kintex ultrascale plus family to xilinx.cpp

* add docs

* combine xcku and xcvu check

* rebuild bitstream for -1 speedgrade

src/board.hpp

@@ -215,6 +215,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("zc706",           "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zcu102",          "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zcu106",          "xczu7evffvc1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("kcu116",          "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zedboard",        "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_10",      "xc7z010clg400",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_20",      "xc7z020clg400",  "digilent", 0, 0, CABLE_DEFAULT)

src/mcsParser.cpp

@@ -43,6 +43,7 @@ int McsParser::parse()
 {
 	string str;
 	istringstream lineStream(_raw_data);
+	_bit_data.resize(_file_size);
 
 	while (std::getline(lineStream, str, '\n')) {
 		char *ptr;

src/part.hpp

@@ -65,6 +65,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
+	{0x04a62093, {"xilinx", "kintexusp", "xcku5p", 6}},
 	{0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}},
 
 	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},

src/xilinx.cpp

@@ -59,7 +59,8 @@ static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
 			"default",
 			{
 				{ "USER1",       {0x02} },
-				{ "CFG_IN",      {0x05}},
+				{ "USER2",       {0x03} },
+				{ "CFG_IN",      {0x05} },
 				{ "USERCODE",    {0x08} },
 				{ "IDCODE",      {0x09} },
 				{ "ISC_ENABLE",  {0x10} },
@@ -169,7 +170,7 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_secondary_file_extension = secondary_filename.substr(
 			secondary_filename.find_last_of(".") + 1);
 		_mode = Device::SPI_MODE;
-		if (_device_package != "xcvu9p-flga2104") {
+		if (!(_device_package == "xcvu9p-flga2104" || _device_package == "xcku5p-ffvb676")) {
 			throw std::runtime_error("Error: secondary flash unavailable");
 		}
 	}
@@ -198,6 +199,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEX_FAMILY;
 	} else if (family == "kintexus") {
 		_fpga_family = KINTEXUS_FAMILY;
+	} else if (family == "kintexusp") {
+		_fpga_family = KINTEXUSP_FAMILY;
 	} else if (family == "artixusp") {
 		_fpga_family = ARTIXUSP_FAMILY;
 	} else if (family == "virtexusp") {

src/xilinx.hpp

@@ -161,6 +161,7 @@ class Xilinx: public Device, SPIInterface {
 			ARTIX_FAMILY,
 			KINTEX_FAMILY,
 			KINTEXUS_FAMILY,
+			KINTEXUSP_FAMILY,
 			ZYNQ_FAMILY,
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,