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openFPGALoader
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Add xcau15p (xcau15p_ffvb676) support (#547) 

Co-authored-by: vbuitvydas <v.buitvydas@limemicro.com>
This commit is contained in:
Tomserv-512 2025-05-10 08:02:21 +03:00 committed by GitHub
parent 4553bacb05
commit 40a588fb2c
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GPG Key ID: B5690EEEBB952194
5 changed files with 14 additions and 2 deletions
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3
spiOverJtag/Makefile
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@ -18,7 +18,8 @@ XILINX_PARTS := xc3s500evq100 \
xc7vx330tffg1157 \ xc7vx330tffg1157 \
xcku040-ffva1156 xcku060-ffva1156 \ xcku040-ffva1156 xcku060-ffva1156 \
xcku5p-ffvb676 \ xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892 xcvu9p-flga2104 xcvu37p-fsvh2892 \
xcau15p-ffvb676
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \ ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \

5
spiOverJtag/build.py
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@ -67,7 +67,7 @@ elif subpart == "xc6v":
family = "Virtex6" family = "Virtex6"
tool = "ise" tool = "ise"
speed = -1 speed = -1
elif subpart in ["xcvu", "xcku"]: elif subpart in ["xcvu", "xcku", "xcau"]:
family = "Xilinx UltraScale" family = "Xilinx UltraScale"
tool = "vivado" tool = "vivado"
else: else:
@ -126,6 +126,7 @@ if tool in ["ise", "vivado"]:
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892", "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
"xcku3p-ffva676" : "xcku3p_ffva676", "xcku3p-ffva676" : "xcku3p_ffva676",
"xcku5p-ffvb676" : "xcku5p_ffvb676", "xcku5p-ffvb676" : "xcku5p_ffvb676",
"xcau15p-ffvb676" : "xcau15p_ffvb676",
}[part] }[part]
if tool == "ise": if tool == "ise":
cst_type = "UCF" cst_type = "UCF"
@ -189,6 +190,8 @@ if tool in ["ise", "vivado"]:
'paramtype': 'vlogdefine', 'paramtype': 'vlogdefine',
'description': 'secondary flash', 'description': 'secondary flash',
'default': 1} 'default': 1}
elif part == "xcau15p-ffvb676":
tool_options = {'part': part + '-2-e'}
else: else:
tool_options = {'part': part + '-1'} tool_options = {'part': part + '-1'}
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower() cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()

7
spiOverJtag/constr_xcau15p_ffvb676.xdc Normal file
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@ -0,0 +1,7 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block

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spiOverJtag/spiOverJtag_xcau15p-ffvb676.bit.gz Normal file
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1
spiOverJtag/xilinx_spiOverJtag.v
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@ -73,6 +73,7 @@ module spiOverJtag
end end
`ifdef xilinxultrascale `ifdef xilinxultrascale
assign sck = drck;
wire [3:0] di; wire [3:0] di;
assign wpn_dq2 = 1'b1; assign wpn_dq2 = 1'b1;
assign hldn_dq3 = 1'b1; assign hldn_dq3 = 1'b1;