README: add note for default behavior (memory/flash) and offset option
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@ -165,6 +165,9 @@ To have complete help
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### Generic usage
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- when a bitstream file is compatible with both memory load and FLASH write, the default behavior is to load bitstream in memory
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- with FPGA using an external SPI flash (*xilinx*, *lattice ECP5/nexus/ice40*, *anlogic*, *efinix*) option **-o** allows one to write raw binary file to an arbitrary adress in FLASH.
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#### display FPGA
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With board name:
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