Unused variables (plus some more white space fixes)
This commit is contained in:
Martin Beynon
parent
07752c37e2
commit
393bf1d28b
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@ -21,25 +21,25 @@
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#include "feaparser.hpp"
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/* FEAbits element defines */
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# define FEA_I2C_DG_FIL_EN (1 << 0) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
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# define FEA_I2C_DG_FIL_EN (1 << 0) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
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# define FEA_FLASH_PROT_SEC_SEL (0x7 << 1) /* Flash Protection Sector Selection */
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# define FEA_MY_ASSP_EN (1 << 4) /* MY_ASSP Enabled 0=Disabled (Default), 1=Enabled */
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# define FEA_PROG_PERSIST (1 << 5) /* PROGRAMN Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_INITN_PERSIST (1 << 6) /* INITN Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_DONE_PERSIST (1 << 7) /* DONE Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_JTAG_PERSIST (1 << 8) /* JTAG Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_SSPI_PERSIST (1 << 9) /* Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_I2C_PERSIST (1 << 10) /* I²C Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_MSPI_PERSIST (1 << 11) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_BOOT_SEQ_SEL (0x07 << 12) /* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
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# define FEA_MY_ASSP_EN (1 << 4) /* MY_ASSP Enabled 0=Disabled (Default), 1=Enabled */
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# define FEA_PROG_PERSIST (1 << 5) /* PROGRAMN Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_INITN_PERSIST (1 << 6) /* INITN Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_DONE_PERSIST (1 << 7) /* DONE Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_JTAG_PERSIST (1 << 8) /* JTAG Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_SSPI_PERSIST (1 << 9) /* Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_I2C_PERSIST (1 << 10) /* I²C Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_MSPI_PERSIST (1 << 11) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_BOOT_SEQ_SEL (0x07 << 12) /* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
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# define FEA_I2C_DG_RANGE_SEL (1 << 15) /* I2C deglitch filter range selection on primary I2C port2 0= 8 to 25 ns range (Default) 1= 16 to 50 ns range */
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# define FEA_VERSION_RB_PROT (1 << 16) /* Version Rollback Protection1 0= Disabled (Default) 1= Enabled (Checks if current version of bitstream is similar to the one that is goi>
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# define FEA_RESERVED_ZERO (0xffff << 17)
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# define FEA_VERSION_RB_PROT (1 << 16) /* Version Rollback Protection1 0= Disabled (Default) 1= Enabled */
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# define FEA_RESERVED_ZERO (0xffff << 17)
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/* Feature Row element defines */
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# define FEATURE_CUSTOM_ID (0xffffffff) /* 32 bits of Custom ID code */
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# define FEATURE_CUSTOM_ID (0xffffffff) /* 32 bits of Custom ID code */
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# define FEATURE_TRACE_ID (0xff << 0) /* 8 bits for the user programmable TraceID */
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# define FEATURE_TRACE_ID (0xff << 0) /* 8 bits for the user programmable TraceID */
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# define FEATURE_I2C_SLAVE_ADDR (0xff << 8) /* 8 bits for the user programmable I2C Slave Address */
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# define FEATURE_DUAL_BOOT_ADDR (0xffff << 16) /* 16 bits for Dual boot address (Most significant 16- bit of address for secondary boot from external flash) */
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@ -47,19 +47,19 @@
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# define FEATURE_MASTER_TIMER_CNT (0x0f << 4) /* Master Timer Count */
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# define FEATURE_SLAVE_IDLE_TIMER_CNT (0x0f << 8) /* Slave Idle Timer Count */
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# define FEATURE_SFDP_CONT_FAIL (1 << 14) /* SFDP Continue on Fail */
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# define FEATURE_SFDP_EN (1 << 15) /* SFDP Enable */
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# define FEATURE_SFDP_EN (1 << 15) /* SFDP Enable */
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# define FEATURE_BULK_ERASE_DISABLE (1 << 16) /* No Bulk Erase */
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# define FEATURE_32BIT_SPIM (1 << 17) /* 32-bit SPIM */
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# define FEATURE_MCLK_BYPASS (1 << 18) /* MCLK Bypass */
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# define FEATURE_LSBF (1 << 19) /* LSBF */
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# define FEATURE_RX_EDGE (1 << 20)
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# define FEATURE_TX_EDGE (1 << 21)
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# define FEATURE_CPOL (1 << 22)
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# define FEATURE_CPHA (1 << 23)
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# define FEATURE_LSBF (1 << 19) /* LSBF */
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# define FEATURE_RX_EDGE (1 << 20)
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# define FEATURE_TX_EDGE (1 << 21)
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# define FEATURE_CPOL (1 << 22)
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# define FEATURE_CPHA (1 << 23)
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# define FEATURE_HSE_CLOCK_SEL (0x3 << 24)
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# define FEATURE_EBR_ENABLE (1 << 26)
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# define FEATURE_SSPI_AUTO (1 << 28) /* SSPI Auto */
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# define FEATURE_CPU (1 << 29) /* CPU */
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# define FEATURE_SSPI_AUTO (1 << 28) /* SSPI Auto */
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# define FEATURE_CPU (1 << 29) /* CPU */
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# define FEATURE_CORE_CLK_SEL (0x03 << 30) /* Core Clock Sel */
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@ -108,45 +108,45 @@ void FeaParser::displayHeader()
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}
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printf("]\n");
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printf("\tCore Clock Select : 0x%x\n", (_featuresRow[2] >> 30) & 0x03);
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printf("\tCPU : %d\n",
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printf("\tCore Clock Select : 0x%x\n", (_featuresRow[2] >> 30) & 0x03);
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printf("\tCPU : %d\n",
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((_featuresRow[2] & FEATURE_CPU)? 1 : 0));
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printf("\tSSPI Auto : %s\n",
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printf("\tSSPI Auto : %s\n",
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((_featuresRow[2] & FEATURE_SSPI_AUTO)?"Enabled":"Disabled"));
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printf("\tReserved Zero (1) : 0x%x\n", (_featuresRow[2] >> 27) & 0x01);
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printf("\tEBR Enable : %s\n",
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printf("\tReserved Zero (1) : 0x%x\n", (_featuresRow[2] >> 27) & 0x01);
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printf("\tEBR Enable : %s\n",
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((_featuresRow[2] & FEATURE_EBR_ENABLE)?"Yes":"No"));
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printf("\tHSE Clock Select : 0x%x\n", (_featuresRow[2] >> 24) & 0x03);
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printf("\tCPHA : %s\n",
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printf("\tHSE Clock Select : 0x%x\n", (_featuresRow[2] >> 24) & 0x03);
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printf("\tCPHA : %s\n",
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((_featuresRow[2] & FEATURE_CPHA)?"Enabled":"Disabled"));
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printf("\tCPOL : %s\n",
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printf("\tCPOL : %s\n",
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((_featuresRow[2] & FEATURE_CPOL)?"Enabled":"Disabled"));
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printf("\tTx Edge : %s\n",
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printf("\tTx Edge : %s\n",
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((_featuresRow[2] & FEATURE_TX_EDGE)?"Enabled":"Disabled"));
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printf("\tRx Edge : %s\n",
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printf("\tRx Edge : %s\n",
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((_featuresRow[2] & FEATURE_RX_EDGE)?"Enabled":"Disabled"));
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printf("\tLSBF : %s\n",
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printf("\tLSBF : %s\n",
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((_featuresRow[2] & FEATURE_LSBF)?"Enabled":"Disabled"));
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printf("\tMClock Bypass : %s\n",
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printf("\tMClock Bypass : %s\n",
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((_featuresRow[2] & FEATURE_MCLK_BYPASS)?"Enabled":"Disabled"));
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printf("\t32-bit SPIM : %s\n",
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printf("\t32-bit SPIM : %s\n",
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((_featuresRow[2] & FEATURE_32BIT_SPIM)?"Enabled":"Disabled"));
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printf("\tBulk Erase Disable : %s\n",
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printf("\tBulk Erase Disable : %s\n",
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((_featuresRow[2] & FEATURE_BULK_ERASE_DISABLE)?"Yes":"No"));
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printf("\tSFDP Enable : %s\n",
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printf("\tSFDP Enable : %s\n",
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((_featuresRow[2] & FEATURE_SFDP_EN)?"Yes":"No"));
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printf("\tSFDP Continue on Fail : %s\n",
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((_featuresRow[2] & FEATURE_SFDP_CONT_FAIL)?"Yes":"No"));
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printf("\tReserved Zero (2) : 0x%x\n", (_featuresRow[2] >> 12) & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", (_featuresRow[2] >> 12) & 0x03);
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printf("\tSlave Idle Timer Count: %d\n", (_featuresRow[2] >> 8) & 0x0f);
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printf("\tMaster Timer Count : %d\n", (_featuresRow[2] >> 4) & 0x0f);
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printf("\tMaster Retry Count : %d\n", (_featuresRow[2] >> 2) & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", _featuresRow[2] & 0x03);
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printf("\tMaster Timer Count : %d\n", (_featuresRow[2] >> 4) & 0x0f);
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printf("\tMaster Retry Count : %d\n", (_featuresRow[2] >> 2) & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", _featuresRow[2] & 0x03);
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printf("\tDual Boot Address : 0x%x\n", (_featuresRow[1] >> 16) & 0xffff);
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printf("\tI2C Slave Address : 0x%x\n", (_featuresRow[1] >> 8) & 0xff);
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printf("\tCustom Trace ID : 0x%x\n", _featuresRow[1] & 0xff);
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printf("\tCustom ID Code : 0x%x\n", _featuresRow[0]);
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printf("\tDual Boot Address : 0x%x\n", (_featuresRow[1] >> 16) & 0xffff);
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printf("\tI2C Slave Address : 0x%x\n", (_featuresRow[1] >> 8) & 0xff);
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printf("\tCustom Trace ID : 0x%x\n", _featuresRow[1] & 0xff);
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printf("\tCustom ID Code : 0x%x\n", _featuresRow[0]);
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printf("\nFEAbits: [0x%08x]\n", _feabits);
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@ -156,7 +156,7 @@ void FeaParser::displayHeader()
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printf("\tI2C Deglitch Range : %s\n",
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((_feabits & FEA_I2C_DG_RANGE_SEL)?"(1) 16 to 50 ns":"(0) 8 to 25 ns"));
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int boot_mode = (_feabits >> 12) & 0x07;
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printf("\tBoot Mode : ");
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printf("\tBoot Mode : ");
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if ((_feabits & FEA_MSPI_PERSIST) == 0) {
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if (boot_mode == 0)
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printf("Dual Boot, CFG0 - CFG1\n");
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@ -190,25 +190,25 @@ void FeaParser::displayHeader()
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else
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printf("Unknown boot sequence selection");
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}
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printf("\tMSPI Enable : %s\n",
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printf("\tMSPI Enable : %s\n",
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((_feabits & FEA_MSPI_PERSIST)?"Yes":"No"));
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printf("\tI2C Disable : %s\n",
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printf("\tI2C Disable : %s\n",
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((_feabits & FEA_I2C_PERSIST)?"Yes":"No"));
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printf("\tSSPI Disable : %s\n",
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printf("\tSSPI Disable : %s\n",
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((_feabits & FEA_SSPI_PERSIST)?"Yes":"No"));
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printf("\tJTAG Disable : %s\n",
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printf("\tJTAG Disable : %s\n",
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((_feabits & FEA_JTAG_PERSIST)?"Yes":"No"));
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printf("\tDONE Enable : %s\n",
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printf("\tDONE Enable : %s\n",
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((_feabits & FEA_DONE_PERSIST)?"Yes":"No"));
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printf("\tINIT Enable : %s\n",
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printf("\tINIT Enable : %s\n",
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((_feabits & FEA_INITN_PERSIST)?"Yes":"No"));
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printf("\tPROGRAM Disable : %s\n",
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printf("\tPROGRAM Disable : %s\n",
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((_feabits & FEA_PROG_PERSIST)?"Yes":"No"));
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printf("\tCustom ID Enable : %s\n",
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printf("\tCustom ID Enable : %s\n",
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((_feabits & FEA_MY_ASSP_EN)?"Yes":"No"));
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int flash_prot = (_feabits >> 1) & 0x07;
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printf("\tFlash Protection : ");
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printf("\tFlash Protection : ");
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if (flash_prot == 0) {
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printf("None\n");
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} else {
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@ -249,11 +249,9 @@ void FeaParser::parseFeatureRowAndFeabits(const vector<string> &content)
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int FeaParser::parse()
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{
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_ss.str(_raw_data);
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std::vector<string>lines;
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int first_pos;
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char instr;
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_ss.str(_raw_data);
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lines = readFeaFile();
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/* empty or end of file */
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@ -25,19 +25,19 @@
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using namespace std;
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#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
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# define ISC_ENABLE_FLASH_MODE (1 << 3)
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# define ISC_ENABLE_SRAM_MODE (0 << 3)
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#define ISC_ENABLE_TRANSPARANT 0x74 /* This command is used to put the device in transparent mode */
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#define ISC_DISABLE 0x26 /* ISC_DISABLE */
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#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
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# define ISC_ENABLE_FLASH_MODE (1 << 3)
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# define ISC_ENABLE_SRAM_MODE (0 << 3)
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#define ISC_ENABLE_TRANSPARANT 0x74 /* This command is used to put the device in transparent mode */
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#define ISC_DISABLE 0x26 /* ISC_DISABLE */
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#define READ_DEVICE_ID_CODE 0xE0 /* IDCODE_PUB */
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#define FLASH_ERASE 0x0E /* ISC_ERASE */
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#define FLASH_ERASE 0x0E /* ISC_ERASE */
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/* Flash areas as defined for Lattice MachXO3L/LF */
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# define FLASH_ERASE_UFM (1<<3)
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# define FLASH_ERASE_CFG (1<<2)
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# define FLASH_ERASE_FEATURE (1<<1)
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# define FLASH_ERASE_CFG (1<<2)
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# define FLASH_ERASE_FEATURE (1<<1)
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# define FLASH_ERASE_SRAM (1<<0)
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# define FLASH_ERASE_ALL 0x0F
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# define FLASH_ERASE_ALL 0x0F
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/* Flash areas as defined for Lattice MachXO3D, used with command: ISC_ERASE */
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# define FLASH_SEC_CFG0 (1<<8)
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# define FLASH_SEC_CFG1 (1<<9)
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@ -57,9 +57,9 @@ using namespace std;
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* This is document is more correct:
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* fpga-tn-02119-1-1-using-hardened-control-functions-machxo3d-reference.pdf
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*/
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#define RESET_CFG_ADDR 0x46 /* LSC_INIT_ADDRESS */
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#define RESET_CFG_ADDR 0x46 /* LSC_INIT_ADDRESS */
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/* Set the Page Address pointer to the Flash page specified */
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#define LSC_WRITE_ADDRESS 0xB4
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#define LSC_WRITE_ADDRESS 0xB4
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# define FLASH_SET_ADDR_CFG0 0x00
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# define FLASH_SET_ADDR_UFM0 0x01
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# define FLASH_SET_ADDR_FEA 0x03
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@ -74,31 +74,31 @@ using namespace std;
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/* Set the Page Address Pointer to the beginning of the UFM sectors.
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* It appears that this function is required when setting address to UFM sectors
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* The LSC_INIT_ADDRESS doesn't work when the sector is set to UFMx ... */
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#define LSC_INIT_ADDR_UFM 0x47
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#define LSC_INIT_ADDR_UFM 0x47
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# define FLASH_UFM_ADDR_UFM0 (1<<10)
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# define FLASH_UFM_ADDR_UFM1 (1<<11)
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# define FLASH_UFM_ADDR_UFM2 (1<<12)
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# define FLASH_UFM_ADDR_UFM3 (1<<13)
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#define PROG_CFG_FLASH 0x70 /* LSC_PROG_INCR_NV */
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#define READ_BUSY_FLAG 0xF0 /* LSC_CHECK_BUSY */
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#define PROG_CFG_FLASH 0x70 /* LSC_PROG_INCR_NV */
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#define READ_BUSY_FLAG 0xF0 /* LSC_CHECK_BUSY */
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/* The busy flag defines bit 7 as busy, but busy flags returns 1 for busy (bit 0). */
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#define REG_CFG_FLASH 0x73 /* LSC_READ_INCR_NV */
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#define PROG_FEATURE_ROW 0xE4 /* LSC_PROG_FEATURE */
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#define REG_CFG_FLASH 0x73 /* LSC_READ_INCR_NV */
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#define PROG_FEATURE_ROW 0xE4 /* LSC_PROG_FEATURE */
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#define READ_FEATURE_ROW 0xE7 /* LSC_READ_FEATURE */
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/* See feaParser.hpp for FEATURE definitions */
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#define PROG_FEABITS 0xF8 /* LSC_PROG_FEABITS */
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#define PROG_FEABITS 0xF8 /* LSC_PROG_FEABITS */
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#define READ_FEABITS 0xFB /* LSC_READ_FEABITS */
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/* See feaParser.hpp for FEAbit definitions */
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#define PROG_DONE 0x5E /* ISC_PROGRAM_DONE - This command is used to program the done bit */
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#define REFRESH 0x79 /* LSC_REFRESH */
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#define PROG_DONE 0x5E /* ISC_PROGRAM_DONE - This command is used to program the done bit */
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#define REFRESH 0x79 /* LSC_REFRESH */
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#define READ_STATUS_REGISTER 0x3C /* LSC_READ_STATUS */
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# define REG_STATUS_DONE (1 << 8) /* Flash or SRAM Done Flag (ISC_EN=0 -> 1 Successful Flash to SRAM transfer, ISC_EN=1 -> 1 Programmed) */
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# define REG_STATUS_ISC_EN (1 << 9) /* Enable Configuration Interface (1=Enable, 0=Disable) */
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# define REG_STATUS_BUSY (1 << 12) /* Busy Flag (1 = Busy) */
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# define REG_STATUS_FAIL (1 << 13) /* Fail Flag (1 = Operation failed) */
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# define REG_STATUS_PP_CFG (1 << 15) /* Password Protection All Enabled for CFG0 and CFG1 flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_FSK (1 << 16) /* Password Protection Enabled for Feature and Security Key flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_UFM (1 << 17) /* Password Protection enabled for all UFM flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_DONE (1 << 8) /* Flash or SRAM Done Flag (ISC_EN=0 -> 1 Successful Flash to SRAM transfer, ISC_EN=1 -> 1 Programmed) */
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# define REG_STATUS_ISC_EN (1 << 9) /* Enable Configuration Interface (1=Enable, 0=Disable) */
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# define REG_STATUS_BUSY (1 << 12) /* Busy Flag (1 = Busy) */
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# define REG_STATUS_FAIL (1 << 13) /* Fail Flag (1 = Operation failed) */
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# define REG_STATUS_PP_CFG (1 << 15) /* Password Protection All Enabled for CFG0 and CFG1 flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_FSK (1 << 16) /* Password Protection Enabled for Feature and Security Key flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_UFM (1 << 17) /* Password Protection enabled for all UFM flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */
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# define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */
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# define REG_STATUS_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */
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@ -122,15 +122,15 @@ using namespace std;
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# define REG_STATUS1_MSPI_PERS (1 << 20) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS1_I2C_DG_FILTER (1 << 21) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS1_I2C_DG_RANGE (1 << 22) /* I2C deglitch filter range selection on primary I2C port 0= 8 to 25 ns range (Default), 1= 16 to 50 ns range */
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#define PROG_ECDSA_PUBKEY0 0x59 /* This command is used to program the first 128 bits of the ECDSA Public Key. */
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#define READ_ECDSA_PUBKEY0 0x5A /* This command is used to read the first 128 bits of the ECDSA Public Key. */
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#define PROG_ECDSA_PUBKEY1 0x5B /* This command is used to program the second 128 bits of the ECDSA Public Key. */
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#define READ_ECDSA_PUBKEY1 0x5C /* This command is used to read the second 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY2 0x61 /* This command is used to program the third 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY2 0x62 /* This command is used to read the third 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY3 0x63 /* This command is used to program the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY3 0x64 /* This command is used to read the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define ISC_NOOP 0xff /* This command is no operation command (NOOP) or null operation. */
|
||||
#define PROG_ECDSA_PUBKEY0 0x59 /* This command is used to program the first 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY0 0x5A /* This command is used to read the first 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY1 0x5B /* This command is used to program the second 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY1 0x5C /* This command is used to read the second 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY2 0x61 /* This command is used to program the third 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY2 0x62 /* This command is used to read the third 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY3 0x63 /* This command is used to program the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY3 0x64 /* This command is used to read the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define ISC_NOOP 0xff /* This command is no operation command (NOOP) or null operation. */
|
||||
|
||||
Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
|
||||
Device::prog_type_t prg_type, std::string flash_sector, bool verify, int8_t verbose):
|
||||
|
|
@ -1385,7 +1385,7 @@ bool Lattice::programFeabits_MachXO3D(uint32_t feabits)
|
|||
|
||||
if (_verify) {
|
||||
for(int i = 0; i < 4; i++) {
|
||||
if ((feabits >> (8*i)) & 0xff != rx[i]) {
|
||||
if (((feabits >> (8*i)) & 0xff) != rx[i]) {
|
||||
printf("\tVerify Failed...\n");
|
||||
return false;
|
||||
}
|
||||
|
|
@ -1533,9 +1533,7 @@ bool Lattice::program_fea_MachXO3D()
|
|||
|
||||
bool Lattice::program_intFlash_MachXO3D()
|
||||
{
|
||||
bool err, ufm_flag;
|
||||
uint64_t featuresRow;
|
||||
uint16_t feabits;
|
||||
bool err;
|
||||
uint32_t erase_op = 0, prog_op = 0;
|
||||
vector<string> data;
|
||||
int offset, fuse_count;
|
||||
|
|
@ -1570,7 +1568,7 @@ bool Lattice::program_intFlash_MachXO3D()
|
|||
/* this is the size of an CFGx+UFMx area in bits (hence the / 128) */
|
||||
fuse_count = _jed.get_fuse_count() / 128;
|
||||
|
||||
for (int i = 0; i < _jed.nb_section(); i++) {
|
||||
for (size_t i = 0; i < _jed.nb_section(); i++) {
|
||||
std::string area_name;
|
||||
|
||||
data = _jed.data_for_section(i);
|
||||
|
|
@ -1583,7 +1581,6 @@ bool Lattice::program_intFlash_MachXO3D()
|
|||
|
||||
erase_op = 0;
|
||||
prog_op = 0;
|
||||
ufm_flag = false;
|
||||
|
||||
/* if the offset > total fuse count, then this file must be configured
|
||||
* for the 2nd config sector (CFG1), so adjust offset */
|
||||
|
|
@ -1634,7 +1631,6 @@ bool Lattice::program_intFlash_MachXO3D()
|
|||
prog_op = FLASH_UFM_ADDR_UFM1;
|
||||
area_name = "EBR (UFM1)";
|
||||
}
|
||||
ufm_flag = true;
|
||||
}
|
||||
else {
|
||||
/* NOT SUPPORTING NON-ZERO OFFSET WRITES...*/
|
||||
|
|
@ -1697,7 +1693,6 @@ bool Lattice::program_intFlash_MachXO3D()
|
|||
}
|
||||
area_name = "UFM3";
|
||||
}
|
||||
ufm_flag = true;
|
||||
}
|
||||
else {
|
||||
printf("Processing CFG data (offset: %d (0x%x))\n", offset, offset);
|
||||
|
|
|
|||
Loading…
Reference in New Issue