latticeSSPI: uses registers struct for status
This commit is contained in:
Gwenhael Goavec-Merou
parent
dede406ebc
commit
319c08e841
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@ -10,7 +10,10 @@
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#define __STDC_FORMAT_MACROS
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#include <cinttypes>
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#include <iomanip>
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#include <iostream>
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#include <list>
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#include <sstream>
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#include <string>
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#include "device.hpp"
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@ -284,76 +287,85 @@ void LatticeSSPI::program(unsigned int /*offset*/, bool /*unprotect_flash*/)
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throw std::exception();
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}
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typedef struct {
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std::string description;
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uint8_t offset;
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uint8_t size;
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std::map<int, std::string> reg_cnt;
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} reg_struct_t;
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#define REG_ENTRY(_description, _offset, _size, ...) \
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{_description, _offset, _size, {__VA_ARGS__}}
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static const std::map<std::string, std::list<reg_struct_t>> reg_content = {
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{"StatusRegister", std::list<reg_struct_t>{
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REG_ENTRY("Transparent Mode", 0, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Config Target Selection", 1, 3, {0, "SRAM array"}, {1, "Efuse"}),
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REG_ENTRY("JTAG Active", 4, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("PWD Protect", 5, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Decrypt Enable", 7, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Done", 8, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("ISC Enable", 9, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Write Enable", 11, 1, {0, "Not Writable"}, {1, "Writable"}),
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REG_ENTRY("Read Enable", 11, 1, {0, "Not Readable"}, {1, "Readable"}),
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REG_ENTRY("Busy Flag", 12, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Fail Flag", 13, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("FFEA OTP", 14, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Decrypt Only", 15, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("PWD Enable", 16, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Std Preamble", 20, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("SPIm Fail1", 21, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("BSE Error Code", 22, 3,
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{ 0, "No err"},
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{ 1, "ID ERR"},
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{ 2, "CMD ERR"},
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{ 3, "CRC ERR"},
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{ 4, "Preamble ERR"},
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{ 5, "Abort ERR"},
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{ 6, "Overflow ERR"},
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{ 7, "SDM EOF"},
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{ 8, "Authentication ERR"},
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{ 9, "Authentication Setup ERR"},
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{10, "Bitstream Engine Timeout ERR"}),
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REG_ENTRY("EXEC Error", 26, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Device failed to verify", 27, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Invalid Command", 28, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("SED Error", 29, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Bypass Mode", 30, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("FT Mode", 31, 1, {0, "No"}, {1, "Yes"}),
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}},
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};
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void LatticeSSPI::displayReadReg(uint32_t dev)
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{
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printf("displayReadReg 0x%08x\n", dev);
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if (dev & 1<<0) printf("\tTRAN Mode\n");
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printf("\tConfig Target Selection : %" PRIx32 "\n", (dev >> 1) & 0x07);
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if (dev & 1<<4) printf("\tJTAG Active\n");
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if (dev & 1<<5) printf("\tPWD Protect\n");
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if (dev & 1<<6) printf("\tOTP\n");
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if (dev & 1<<7) printf("\tDecrypt Enable\n");
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if (dev & REG_STATUS_DONE) printf("\tDone Flag\n");
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if (dev & REG_STATUS_ISC_EN) printf("\tISC Enable\n");
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if (dev & 1 << 10) printf("\tWrite Enable\n");
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if (dev & 1 << 11) printf("\tRead Enable\n");
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if (dev & REG_STATUS_BUSY) printf("\tBusy Flag\n");
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if (dev & REG_STATUS_FAIL) printf("\tFail Flag\n");
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if (dev & 1 << 14) printf("\tFFEA OTP\n");
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if (dev & 1 << 15) printf("\tDecrypt Only\n");
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if (dev & 1 << 16) printf("\tPWD Enable\n");
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if (dev & 1 << 17) printf("\tUFM OTP\n");
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if (dev & 1 << 18) printf("\tASSP\n");
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if (dev & 1 << 19) printf("\tSDM Enable\n");
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if (dev & 1 << 20) printf("\tEncryption PreAmble\n");
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if (dev & 1 << 21) printf("\tStd PreAmble\n");
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if (dev & 1 << 22) printf("\tSPIm Fail1\n");
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const uint8_t err = (dev >> 23)&0x07;
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printf("\tBSE Error Code\n");
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printf("\t\t");
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switch (err) {
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case 0:
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printf("No err\n");
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break;
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case 1:
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printf("ID ERR\n");
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break;
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case 2:
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printf("CMD ERR\n");
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break;
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case 3:
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printf("CRC ERR\n");
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break;
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case 4:
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printf("Preamble ERR\n");
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break;
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case 5:
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printf("Abort ERR\n");
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break;
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case 6:
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printf("Overflow ERR\n");
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break;
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case 7:
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printf("SDM EOF\n");
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break;
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case 8:
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printf("Authentication ERR\n");
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break;
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case 9:
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printf("Authentication Setup ERR\n");
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break;
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case 10:
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printf("Bitstream Engine Timeout ERR\n");
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break;
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default:
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printf("unknown error: %x\n", err);
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auto reg = reg_content.find("StatusRegister");
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if (reg == reg_content.end()) {
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printError("Unknown register StatusRegister");
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return;
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}
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if (dev & REG_STATUS_EXEC_ERR) printf("\tEXEC Error\n");
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if ((dev >> 27) & 0x01) printf("\tDevice failed to verify\n");
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if ((dev >> 28) & 0x01) printf("\tInvalid Command\n");
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if ((dev >> 29) & 0x01) printf("\tSED Error\n");
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if ((dev >> 30) & 0x01) printf("\tBypass Mode\n");
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if ((dev >> 31) & 0x01) printf("\tFT Mode\n");
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std::stringstream raw_val;
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raw_val << "0x" << std::hex << dev;
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printSuccess("Register raw value: " + raw_val.str());
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const std::list<reg_struct_t> regs = reg->second;
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for (reg_struct_t r: regs) {
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uint8_t offset = r.offset;
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uint8_t size = r.size;
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uint32_t mask = (1 << size) - 1;
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uint32_t val = (dev >> offset) & mask;
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std::stringstream ss, desc;
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desc << r.description;
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ss << std::setw(24) << std::left << r.description;
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if (r.reg_cnt.size() != 0) {
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ss << r.reg_cnt[val];
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} else {
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std::stringstream hex_val;
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hex_val << "0x" << std::hex << val;
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ss << hex_val.str();
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}
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printInfo(ss.str());
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}
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}
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