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openFPGALoader
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Sort. Fix pinout constraints.

This commit is contained in:
bl 2023-02-14 03:24:09 +01:00
parent 95586ab86c
commit 2df5a1ae7c
2 changed files with 10 additions and 18 deletions
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6
spiOverJtag/constr_xc6v_ff784.ucf
View File

@ -1,6 +1,2 @@
CONFIG VCCAUX = "2.5";
NET "sdi_dq0" LOC = H6 | IOSTANDARD = LVCMOS25;
NET "sdo_dq1" LOC = AF6 | IOSTANDARD = LVCMOS25;
NET "sdo_dq1" LOC = AF24 | IOSTANDARD = LVCMOS25;
NET "csn" LOC = AE24 | IOSTANDARD = LVCMOS25;
NET "sck" LOC = AH6 | IOSTANDARD = LVCMOS25;

22
spiOverJtag/xilinx_spiOverJtag.v
View File

@ -2,10 +2,6 @@ module spiOverJtag
(
`ifndef virtexultrascale
output csn,
`ifdef spartan6
output sck,
`endif
`ifdef spartan3e
output sck,
`endif
@ -91,21 +87,21 @@ module spiOverJtag
STARTUP_VIRTEX6 #(
.PROG_USR("FALSE")
) startup_virtex6_inst (
.EOS(),
.CFGCLK(), // unused
.CFGMCLK(), // unused
.CLK(1'b0), // unused
.DINSPI(di), // data from SPI flash
.EOS(),
.GSR(1'b0), // unused
.GTS(1'b0), // unused
.KEYCLEARB(1'b0), // not used
.PACK(1'b0), // tied low for 'safe' operations
.PREQ(), // unused
.TCKSPI(), // echo of CCLK from TCK pin
.USRCCLKO (sck), // user FPGA -> CCLK pin
.USRCCLKTS(1'b0), // drive CCLK not in high-Z
.USRDONEO (1'b1), // why both USRDONE are high?
.USRDONETS(1'b1), // ??
.TCKSPI(), // echo of CCLK from TCK pin
.DINSPI(di), // data from SPI flash
.CFGMCLK(), // unused
.CFGCLK(), // unused
.PREQ(), // unused
.PACK(1'b0), // tied low for 'safe' operations
.KEYCLEARB(1'b0) // not used
.USRDONETS(1'b1) // ??
);
`endif
`else // virtexultrascale