xilinx: added readback access to registers (stat, conf, ...)
This commit is contained in:
Gwenhael Goavec-Merou
parent
99147efa27
commit
2dd2f45e61
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@ -41,6 +41,8 @@ class Device {
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virtual void program(unsigned int offset,
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bool unprotect_flash) = 0;
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virtual bool read_register(const std::string reg_name) { return false;}
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/**********************/
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/* flash access */
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/**********************/
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21
src/main.cpp
21
src/main.cpp
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@ -94,6 +94,7 @@ struct arguments {
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std::map<uint32_t, misc_device> user_misc_devs;
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bool read_dna;
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bool read_xadc;
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string read_register;
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};
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int run_xvc_server(const struct arguments &args, const cable_t &cable,
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@ -123,7 +124,7 @@ int main(int argc, char **argv)
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/* xvc server */
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false, 3721, "-",
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"", false, {}, // mcufw conmcu, user_misc_dev_list
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false, false // read_dna, read_xadc
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false, false, "" // read_dna, read_xadc, read_register
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};
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/* parse arguments */
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try {
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@ -612,6 +613,11 @@ int main(int argc, char **argv)
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fpga->connectJtagToMCU();
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}
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/* read internal register */
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if (!args.read_register.empty()) {
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fpga->read_register(args.read_register);
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}
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/* unprotect SPI flash */
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if (args.unprotect_flash && args.bit_file.empty()) {
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fpga->unprotect_flash();
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@ -701,7 +707,7 @@ static int parse_eng(string arg, double *dst) {
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int parse_opt(int argc, char **argv, struct arguments *args,
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jtag_pins_conf_t *pins_config)
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{
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string freqo;
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string freqo, rd_reg;
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vector<string> pins, bus_dev_num;
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bool verbose, quiet;
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int8_t verbose_level = -2;
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@ -831,6 +837,8 @@ int parse_opt(int argc, char **argv, struct arguments *args,
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cxxopts::value<bool>(args->read_dna))
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("X,read_xadc", "Read XADC (Xilinx FPGA only)",
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cxxopts::value<bool>(args->read_xadc))
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("read-register", "Read Status Register(Xilinx FPGA only)",
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cxxopts::value<string>(rd_reg))
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("V,Version", "Print program version");
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options.parse_positional({"bitstream"});
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@ -1017,6 +1025,12 @@ int parse_opt(int argc, char **argv, struct arguments *args,
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printf("pas empty\n");
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}
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if (result.count("read-register")) {
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args->read_register = rd_reg;
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printf("read_register");
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std::cout << args->read_register << std::endl;
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}
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if (args->bit_file.empty() &&
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args->secondary_bit_file.empty() &&
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args->file_type.empty() &&
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@ -1030,7 +1044,8 @@ int parse_opt(int argc, char **argv, struct arguments *args,
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!args->reset &&
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!args->conmcu &&
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!args->read_dna &&
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!args->read_xadc) {
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!args->read_xadc &&
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args->read_register.empty()) {
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printError("Error: bitfile not specified");
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cout << options.help() << endl;
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throw std::exception();
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222
src/xilinx.cpp
222
src/xilinx.cpp
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@ -8,7 +8,10 @@
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#include <unistd.h>
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#include <cstring>
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#include <fstream>
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#include <iomanip>
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#include <iostream>
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#include <list>
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#include <memory>
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#include <stdexcept>
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#include <string>
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@ -131,6 +134,7 @@ static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
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{
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{ "USER1", {0x02} },
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{ "USER2", {0x03} },
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{ "CFG_OUT", {0x04} },
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{ "CFG_IN", {0x05} },
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{ "USERCODE", {0x08} },
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{ "IDCODE", {0x09} },
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@ -807,8 +811,222 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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* now functional. X 1 3
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*/
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_jtag->go_test_logic_reset();
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/* Some xc7s50 does not detect correct connected flash w/o this shift*/
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_jtag->shiftIR(tx_buf, rx_buf, _irlen);
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/* Some xc7s50 does not detect correct connected flash w/o this shift*/
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_jtag->shiftIR(tx_buf, rx_buf, _irlen);
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uint8_t ir_c = rx_buf[0] & 0x03;
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uint8_t isc_done = ((rx_buf[0] >> 2) & 0x01);
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uint8_t isc_ena = ((rx_buf[0] >> 3) & 0x01);
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uint8_t init = ((rx_buf[0] >> 4) & 0x01);
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uint8_t done = ((rx_buf[0] >> 5) & 0x01);
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printf("Shift IR %02x\n", rx_buf[0]);
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printf("ir: %x isc_done %x isc_ena %x init %x done %x\n", ir_c, isc_done, isc_ena,
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init, done);
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if (!done) {
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read_register("STAT");
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}
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}
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static const uint32_t reverseByte(uint32_t in) {
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uint8_t out [4];
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for (int i = 0; i < 4; i++) {
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uint8_t tmp = (in >> (i*8)) & 0xff;
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out[i] = BitParser::reverseByte(tmp);
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}
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return ((((uint32_t)out[0]) << 24) |
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(((uint32_t)out[1]) << 16) |
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(((uint32_t)out[2]) << 8) |
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(((uint32_t)out[3]) << 0));
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}
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static const uint32_t reverseWord(uint32_t in) {
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uint32_t out = 0;
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for (int i = 0; i < 32; i++) {
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out <<= 1;
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out |= (in >> i) & 0x01;
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}
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return out;
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}
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static const uint32_t char_array_to_word(uint8_t *in)
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{
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return (((uint32_t)in[3] << 24) |
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((uint32_t)in[2] << 16) |
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((uint32_t)in[1] << 8) |
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((uint32_t)in[0] << 0));
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}
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typedef struct {
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std::string description;
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uint8_t offset;
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uint8_t size;
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std::map<int, std::string> reg_cnt;
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} reg_struct_t;
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#define REG_ENTRY(_description, _offset, _size, ...) \
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{_description, _offset, _size, {__VA_ARGS__}}
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static const std::map<std::string, std::list<reg_struct_t>> reg_content = {
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{"CTRL0", std::list<reg_struct_t>{
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REG_ENTRY("GTS USR B", 0, 1,
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{0, "I/Os 3-stated"}, {1, "I/Os active"}),
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REG_ENTRY("Reserved", 1, 2),
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REG_ENTRY("PERSIST", 3, 1,
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{0, "No"}, {1, "Yes"}),
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REG_ENTRY("SBITS", 4, 2,
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{0, "Read/Write OK"}, {1, "Readback disabled"},
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{2, "Both Writes and Reads disabled"},
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{3, "Both Writes and Reads disabled"}),
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REG_ENTRY("DEC", 6, 1,
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{0, "Disable"}, {1, "Enable"}),
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REG_ENTRY("FARSRC", 7, 1),
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REG_ENTRY("GLUMASK B", 8, 1),
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REG_ENTRY("Reserved", 9, 1),
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REG_ENTRY("ConfigFallback", 10, 1,
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{0, "Disable"}, {1, "Enable"}),
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REG_ENTRY("Reserved", 11, 1),
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REG_ENTRY("OverTempPwrDown",12, 1,
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{0, "Disable"}, {1, "Enable"}),
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REG_ENTRY("Reserved", 13, 17),
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REG_ENTRY("ICAP Select", 30, 1,
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{0, "Top ICAPE2 Port Enabled"},
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{1, "Bottom ICAPE2 Port Enabled"}),
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REG_ENTRY("EFUSE key", 31, 1,
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{0, "Battery backed RAM"}, {1, "eFUSE"}),
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}},
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{"STAT", std::list<reg_struct_t>{
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REG_ENTRY("CRC Error", 0, 1,
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{0, "No CRC error"}, {1, "CRC error"}),
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REG_ENTRY("Part Secured", 1, 1),
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REG_ENTRY("MMCM lock", 2, 1),
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REG_ENTRY("DCI match", 3, 1),
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REG_ENTRY("EOS", 4, 1),
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REG_ENTRY("GTS CFG B", 5, 1),
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REG_ENTRY("GWE", 6, 1),
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REG_ENTRY("GHIGH B", 7, 1),
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REG_ENTRY("MODE", 8, 3),
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REG_ENTRY("INIT Complete", 11, 1),
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REG_ENTRY("INIT B", 12, 1),
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REG_ENTRY("Release Done", 13, 1),
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REG_ENTRY("Done", 14, 1),
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REG_ENTRY("ID Error", 15, 1,
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{0, "No ID error"}, {1, "ID error"}),
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REG_ENTRY("DEC Error", 16, 1),
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REG_ENTRY("XADC Over temp", 17, 1),
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REG_ENTRY("STARTUP State", 18, 3),
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REG_ENTRY("Reserved", 21, 4),
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REG_ENTRY("BUS Width", 25, 2,
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{0, "x1"}, {1, "x8"}, {2, "x16"}, {3, "x32"}),
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REG_ENTRY("Reserved", 27, 5)
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}},
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};
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/* UG470 table 5-23 */
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static const std::map<std::string, uint8_t> reg_code = {
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{"CTRL0", 0x05}, // Control register 0
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{"STAT", 0x07}, // Status register
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{"CONF0", 0x09}, // Configuration Option 0
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{"CONF1", 0x0e}, // Configuration Option 1
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{"BHSTAT", 0x16}, // Boot history status register
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{"CTRL1", 0x18}, // Control register 1
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};
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uint32_t Xilinx::dumpRegister(std::string reg_name)
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{
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uint8_t reg[4];
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const uint8_t dummy[] = {0x00, 0x00, 0x00, 0x04};
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/* opcode:
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* 0x0: NOP
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* 0x1: read
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* 0x2: write
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* 0x3: Reserved
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*/
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/* register code
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* 0x05: Control register 0
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* 0x07: Status register
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* 0x09: Configuration Option 0
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* 0x0e: Configuration Option 1
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* 0x18: Control Register 1
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* 0x16: Boot history Status register
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*/
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auto code = reg_code.find(reg_name);
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if (code == reg_code.end()) {
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printError("Unknown register " + reg_name);
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printError("Known Register are:");
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for (auto reg :reg_code)
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printError("\t" + reg.first);
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return 0xdeadbeef;
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}
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/* packet type 1 */
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const uint32_t regcode = static_cast<uint32_t>(code->second);
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uint32_t cfg_packets[] = {
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0xAA995566, // Sync Word
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0x20000000, // NOOP
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((0x01 & 0x0007) << 29) | // [31:29]: Header type
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((0x01 & 0x0003) << 27) | // [28:27]: opcode
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((regcode & 0x3fff) << 13) | // [26:13]: register code
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((0x00 & 0x0003) << 11) | // [12:11]: Reserved must be set to 0
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((0x01 & 0x07ff) << 0), // [10:0 ]: word count
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0x20000000, // NOOP
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0x20000000, // NOOP
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};
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_jtag->go_test_logic_reset();
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->shiftIR(get_ircode(_ircode_map, "CFG_IN"), NULL, _irlen, Jtag::SELECT_DR_SCAN);
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Jtag::tapState_t next_state = Jtag::SHIFT_DR;
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for (int i = 0; i < 5; i++) {
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if (i == 4)
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next_state = Jtag::SELECT_IR_SCAN;
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const uint32_t tmp = reverseWord(cfg_packets[i]);
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const uint8_t cfg[] = {
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static_cast<uint8_t>((tmp >> 0) & 0xff),
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static_cast<uint8_t>((tmp >> 8) & 0xff),
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static_cast<uint8_t>((tmp >> 16) & 0xff),
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static_cast<uint8_t>((tmp >> 24) & 0xff)
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};
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_jtag->shiftDR(cfg, NULL, 32, next_state);
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}
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_jtag->shiftIR(get_ircode(_ircode_map, "CFG_OUT"), NULL, _irlen, Jtag::SELECT_DR_SCAN);
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_jtag->shiftDR(dummy, reg, 32);
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_jtag->go_test_logic_reset();
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uint32_t reg_word = char_array_to_word(reg);
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reg_word = reverseWord(reg_word);
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return reg_word;
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}
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void Xilinx::displayRegister(const std::string reg_name, const uint32_t reg_val) {
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auto reg = reg_content.find(reg_name);
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if (reg == reg_content.end()) {
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printError("Unknown register " + reg_name);
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return;
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}
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std::stringstream raw_val;
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raw_val << "0x" << std::hex << std::to_string(reg_val);
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printSuccess("Register raw value: " + raw_val.str());
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const std::list<reg_struct_t> regs = reg->second;
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for (reg_struct_t r: regs) {
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uint8_t offset = r.offset;
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uint8_t size = r.size;
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uint32_t mask = (1 << size) - 1;
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uint32_t val = (reg_val >> offset) & mask;
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std::stringstream ss, desc;
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desc << r.description;
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ss << std::setw(15) << std::left << r.description;
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if (r.reg_cnt.size() != 0)
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ss << r.reg_cnt[val];
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else
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ss << std::to_string(val);
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printInfo(ss.str());
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}
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}
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bool Xilinx::dumpFlash(uint32_t base_addr, uint32_t len)
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@ -36,6 +36,23 @@ class Xilinx: public Device, SPIInterface {
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void program_mem(ConfigBitstreamParser *bitfile);
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bool dumpFlash(uint32_t base_addr, uint32_t len) override;
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bool read_register(const std::string reg_name) override {
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displayRegister(reg_name, dumpRegister(reg_name));
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return true;
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}
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/*!
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* \brief display register content (bits/slices)
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* \in reg_name: register name
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* \in reg_val: register value
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*/
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void displayRegister(const std::string reg_name, const uint32_t reg_val);
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/*!
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* \brief read register value from the devices
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* \in reg_name: register name
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* \return register value
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*/
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uint32_t dumpRegister(const std::string reg_name);
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/*!
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* \brief protect SPI flash blocks
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*/
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