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spiFlash: fixed set_quad_bit method

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-22 08:53:54 +02:00
parent 24a0548c3e
commit 2a46ab9265
1 changed files with 11 additions and 8 deletions
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19
src/spiFlash.cpp
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@ -622,6 +622,7 @@ void SPIFlash::display_status_reg(uint8_t reg)
printf("IRL : %x\n", ((reg >> 4) & 0x0f)); printf("IRL : %x\n", ((reg >> 4) & 0x0f));
break; break;
case 0x0102: case 0x0102:
case 0x0120:
_spi->spi_put(FLASH_RDCR, NULL, &reg, 1); _spi->spi_put(FLASH_RDCR, NULL, &reg, 1);
printf("\nConfiguration Register\n"); printf("\nConfiguration Register\n");
printf("RDCR : %02x\n", reg); printf("RDCR : %02x\n", reg);
@ -630,6 +631,8 @@ void SPIFlash::display_status_reg(uint8_t reg)
printf("TBPARM : %d\n", ((reg >> 2) & 0x01)); printf("TBPARM : %d\n", ((reg >> 2) & 0x01));
printf("BPNV : %d\n", ((reg >> 3) & 0x01)); printf("BPNV : %d\n", ((reg >> 3) & 0x01));
printf("TBPROT : %d\n", ((reg >> 5) & 0x01)); printf("TBPROT : %d\n", ((reg >> 5) & 0x01));
if (dev_id == 0x0120)
printf("LC : %d\n", ((reg >> 6) & 0x02));
break; break;
case 0x0160: case 0x0160:
_spi->spi_put(FLASH_RDCR, NULL, &reg, 1); _spi->spi_put(FLASH_RDCR, NULL, &reg, 1);
@ -891,11 +894,11 @@ int SPIFlash::enable_protection(uint32_t length)
bool SPIFlash::set_quad_bit(bool set_quad) bool SPIFlash::set_quad_bit(bool set_quad)
{ {
uint8_t reg_wr, reg_rd; // read/write registers code uint8_t reg_wr, reg_rd; // read/write registers code.
uint16_t reg_val; uint16_t reg_val = 0; // set to 0: avoid random when 8bits are read.
uint32_t nb_rd_byte = 1; // Number of bytes to read (may differ from Flash models). uint32_t nb_rd_byte = 1; // read bytes len (may differ from Flash models).
uint32_t nb_wr_byte = 1; // Number of bytes to write. uint32_t nb_wr_byte = 1; // write bytes len.
uint16_t quad_bit = 0; // quad_mask copy when bit must be set uint16_t quad_bit = 0; // quad_mask copy when bit must be set.
if (!_flash_model) { if (!_flash_model) {
printError("spiFlash Error: can't configure Quad mode on unknown SPI Flash"); printError("spiFlash Error: can't configure Quad mode on unknown SPI Flash");
@ -953,7 +956,6 @@ bool SPIFlash::set_quad_bit(bool set_quad)
case CONFR: case CONFR:
uint8_t status = read_status_reg(); uint8_t status = read_status_reg();
reg_val = ((reg_val & 0xff) << 8) | status; reg_val = ((reg_val & 0xff) << 8) | status;
_spi->spi_put(reg_wr, (uint8_t*) &reg_val, NULL, nb_wr_byte);
break; break;
} }
@ -961,15 +963,16 @@ bool SPIFlash::set_quad_bit(bool set_quad)
_spi->spi_put(reg_wr, (uint8_t *)&reg_val, NULL, nb_wr_byte); _spi->spi_put(reg_wr, (uint8_t *)&reg_val, NULL, nb_wr_byte);
/* Wait for completion */ /* Wait for completion */
if (_spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WEL, 0x00, 1000) != 0) { if (_spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WEL, 0x00, 10000) != 0) {
printError("SPIFlash Error: failed to disable write"); printError("SPIFlash Error: failed to disable write");
return false; return false;
} }
/* Check if register is correctly updated */ /* Check if register is correctly updated */
reg_val = 0; // 16 bits but only LSB may be updated
_spi->spi_put(reg_rd, NULL, (uint8_t *)&reg_val, nb_rd_byte); _spi->spi_put(reg_rd, NULL, (uint8_t *)&reg_val, nb_rd_byte);
if ((reg_val & _flash_model->quad_mask) == quad_bit) { if ((reg_val & _flash_model->quad_mask) != quad_bit) {
printf("%04x %04x %04x\n", reg_val, reg_val & _flash_model->quad_mask, quad_bit); printf("%04x %04x %04x\n", reg_val, reg_val & _flash_model->quad_mask, quad_bit);
printError("SPIFlash Error: failed to update Quad bit"); printError("SPIFlash Error: failed to update Quad bit");
return false; return false;