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Add support for Digilent Digital Discovery and Analog Discovery 2 (openFPGALoader -c digilent_ad)

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ultraembedded
2021-06-10 22:38:17 +01:00
parent b1cdcba15e
commit 291f1b6d6f
5 changed files with 7 additions and 1 deletions
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src/cable.hpp
+1
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@@ -32,6 +32,7 @@ static std::map <std::string, cable_t> cable_list = {
{"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}},
{"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80, true}}},
{"dirtyJtag", {MODE_DIRTYJTAG, {}}},
{"efinix_spi", {MODE_FTDI_SERIAL, {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}},
{"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}},
src/ftdipp_mpsse.cpp
+1 -1
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@@ -186,7 +186,7 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode,
buf_cmd[1] = _cable.bit_low_val; // 0xe8;
buf_cmd[2] = _cable.bit_low_dir; // 0xeb;
if (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H) {
if (_cable.force_high_bits || (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H)) {
buf_cmd[4] = _cable.bit_high_val; // 0x00;
buf_cmd[5] = _cable.bit_high_dir; // 0x60;
to_wr = 6;
src/ftdipp_mpsse.hpp
+1
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@@ -13,6 +13,7 @@ class FTDIpp_MPSSE {
int bit_low_dir;
int bit_high_val;
int bit_high_dir;
int force_high_bits;
} mpsse_bit_config;
FTDIpp_MPSSE(const mpsse_bit_config &cable, const std::string &dev,
src/part.hpp
+1
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@@ -22,6 +22,7 @@ static std::map <int, fpga_model> fpga_list = {
{0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}},
{0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}},
{0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}},
{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
{0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}},