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Merge pull request #205 from rstephan/spartan3e 

Spartan3E (xc3s500evq100) and Papilio One
This commit is contained in:
Gwenhael Goavec-Merou 2022-03-28 18:37:43 +02:00 committed by GitHub
parent 1f6432adc7 6da87c3d24
commit 27f0ff2816
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GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 65 additions and 4 deletions
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6
doc/FPGAs.yml
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@ -183,10 +183,12 @@ Xilinx:
Flash: OK
- Description: Spartan 3
Model: xc3s200
Model:
- xc3s200
- xc3s500e
URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html
Memory: OK
Flash: NA
Flash: OK
- Description: Spartan 6
Model:

7
doc/boards.yml
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@ -341,6 +341,13 @@
Flash: OK (DFU)
Constraints: OrangeCrab-r0.2
- ID: papilio_one
Description: Papilio One
URL: https://papilio.cc/index.php?n=Papilio.PapilioOne
FPGA: Spartan3E xc3s500e-vq100
Memory: OK
Flash: OK
- ID: pipistrello
Description: Saanlima Pipistrello LX45
URL: http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello

7
doc/cable.yml
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@ -197,6 +197,13 @@ orbtrace:
URL: https://github.com/orbcode/orbtrace
papilio:
- Name: papilio
Description: Papilio FPGA Platform
URL: https://papilio.cc/
tigard:
- Name: tigard

2
spiOverJtag/Makefile
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@ -1,4 +1,4 @@
XILINX_PARTS := xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
XILINX_PARTS := xc3s500evq100 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
xc6slx150tfgg484 \
xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
xc7a50tcpg236 xc7a75tfgg484 xc7a100tcsg324 xc7a100tfgg484 xc7a200tsbg484 \

10
spiOverJtag/build.py
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@ -44,12 +44,18 @@ elif subpart == "xc7s":
elif subpart == "xc6s":
family = "Spartan6"
tool = "ise"
speed = -3
elif subpart == "xc3s":
family = "Spartan3E"
tool = "ise"
speed = -4
else:
print("Error: unknown device")
os.sys.exit()
if tool in ["ise", "vivado"]:
pkg_name = {
"xc3s500evq100" : "xc3s_vq100",
"xc6slx16ftg256" : "xc6s_ftg256",
"xc6slx16csg324" : "xc6s_csg324",
"xc6slx45csg324" : "xc6s_csg324",
@ -73,18 +79,20 @@ if tool in ["ise", "vivado"]:
cst_type = "UCF"
tool_options = {'family': family,
'device': {
"xc3s500evq100": "xc3s500e",
"xc6slx16ftg256": "xc6slx16",
"xc6slx16csg324": "xc6slx16",
"xc6slx45csg324": "xc6slx45",
"xc6slx100fgg484": "xc6slx100",
"xc6slx150tfgg484": "xc6slx150t"}[part],
'package': {
"xc3s500evq100": "vq100",
"xc6slx16ftg256": "ftg256",
"xc6slx16csg324": "csg324",
"xc6slx45csg324": "csg324",
"xc6slx100fgg484": "fgg384",
"xc6slx150tfgg484": "fgg484"}[part],
'speed' : -3
'speed' : speed
}
else:
cst_type = "xdc"

5
spiOverJtag/constr_xc3s_vq100.ucf Normal file
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@ -0,0 +1,5 @@
NET "sdi_dq0" LOC = P27 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = P44 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = P24 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = P50 | IOSTANDARD = LVCMOS33;

BIN
spiOverJtag/spiOverJtag_xc3s500evq100.bit.gz Normal file
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29
spiOverJtag/xilinx_spiOverJtag.v
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@ -1,8 +1,12 @@
module spiOverJtag
(
output csn,
`ifdef spartan6
output sck,
`endif
`ifdef spartan3e
output sck,
`endif
output sdi_dq0,
input sdo_dq1,
@ -41,6 +45,10 @@ module spiOverJtag
`ifdef spartan6
assign sck = drck;
`else
`ifdef spartan3e
assign sck = drck;
assign runtest = tmp_up_s;
`else
STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
@ -61,7 +69,27 @@ module spiOverJtag
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
);
`endif
`endif
`ifdef spartan3e
BSCAN_SPARTAN3 bscane2_inst (
.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
.DRCK1 (drck), // 1-bit output: Gated TCK output. When SEL
// is asserted, DRCK toggles when
// CAPTURE or SHIFT are asserted.
.DRCK2 (), // 1-bit output: USER2 function
.RESET (), // 1-bit output: Reset output for TAP controller.
.SEL1 (sel), // 1-bit output: USER1 instruction active output.
.SEL2 (), // 1-bit output: USER2 instruction active output.
.SHIFT (), // 1-bit output: SHIFT output from TAP controller.
.TDI (tdi), // 1-bit output: Test Data Input (TDI) output
// from TAP controller.
.UPDATE (update), // 1-bit output: UPDATE output from TAP controller
.TDO1 (tdo), // 1-bit input: Test Data Output (TDO) input
// for USER1 function.
.TDO2 () // 1-bit input: USER2 function
);
`else
`ifdef spartan6
BSCAN_SPARTAN6 #(
`else
@ -88,5 +116,6 @@ module spiOverJtag
.TDO (tdo) // 1-bit input: Test Data Output (TDO) input
// for USER function.
);
`endif
endmodule

1
src/board.hpp
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@ -191,6 +191,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("zc706", "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zcu102", "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("papilio_one", "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT),
};
#endif

1
src/cable.hpp
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@ -63,6 +63,7 @@ static std::map <std::string, cable_t> cable_list = {
{"jlink", {MODE_JLINK, {0x1366, 0x0105, 0, 0, 0, 0, 0 }}},
{"jtag-smt2-nc", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"orbtrace", {MODE_CMSISDAP, {0x1209, 0x3443, 0, 0, 0, 0, 0 }}},
{"papilio", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x09, 0x0B}}},
{"tigard", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0x08, 0x3B, 0x00, 0x00}}},
{"usb-blaster", {MODE_USBBLASTER, {0x09Fb, 0x6001, 0, 0, 0, 0, 0 }}},
{"usb-blasterII", {MODE_USBBLASTER, {0x09Fb, 0x6810, 0, 0, 0, 0, 0 }}},

1
src/part.hpp
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@ -32,6 +32,7 @@ static std::map <int, fpga_model> fpga_list = {
{0x03656093, {"xilinx", "kintex7", "xc7k410t", 6}},
{0x01414093, {"xilinx", "spartan3", "xc3s200", 6}},
{0x01c22093, {"xilinx", "spartan3", "xc3s500e", 6}},
{0x04001093, {"xilinx", "spartan6", "xc6slx9", 6}},
{0x04002093, {"xilinx", "spartan6", "xc6slx16", 6}},