spiOverJtag: Add support for Efinix T120F324

doc/FPGAs.yml

@@ -36,6 +36,7 @@ Efinix:
     Model:
       - T8
       - T13
+      - T120
     URL: https://www.efinixinc.com/products-trion.html
     Memory: NA
     Flash: OK

spiOverJtag/Makefile

@@ -21,7 +21,7 @@ ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
 	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
-EFINIX_PARTS := t8f81 t13f256 ti180j484
+EFINIX_PARTS := t8f81 t13f256 t120f324 ti180j484
 EFINIX_BIT_FILES := $(addsuffix .bit.gz, $(addprefix spiOverJtag_efinix_, $(EFINIX_PARTS)))
 
 BIT_FILES := $(ALTERA_BIT_FILES) $(EFINIX_BIT_FILES) $(XILINX_BIT_FILES)

spiOverJtag/efinix_build.py

@@ -59,6 +59,7 @@ timing_models = {
     "T8F81": "C2",
     "T13F256": "C3",
     "TI180J484": "C3",
+    "T120F324": "C4",
 }
 
 def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
@@ -66,13 +67,23 @@ def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
     # Basic settings
     isf_array = [
         "# Device setting",
+    ]
+
+    if pkg == "F324":
+        # F324 package has 1A and merged 1B_1C IOBank
+        isf_array.extend([
+            "design.set_device_property(\"1A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
+            "design.set_device_property(\"1B_1C\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
+        ])
+    else:
+        isf_array.extend([
             "design.set_device_property(\"1A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
             "design.set_device_property(\"1B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
             "design.set_device_property(\"1C\",\"VOLTAGE\",\"1.1\",\"IOBANK\")",
             "design.set_device_property(\"2A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
             "design.set_device_property(\"2B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
-        "",
+        ])
-    ]
+    isf_array.append("")
 
     # JTAG settings
     isf_array.append("# ---------- JTAG 1 ---------")