spiOverJtag: Add new package xc7a (fbg484) and xc7a200tfbg484 bitstream
Add fbg484 package .xdc constraint file and xc7a200tfbg484 bitstream Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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@ -3,7 +3,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx
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xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
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xc7a50tcsg324 xc7a50tcpg236 xc7a75tfgg484 \
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xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
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xc7a200tsbg484 \
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xc7a200tsbg484 xc7a200tfbg484 \
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xc7s25csga225 xc7s25csga324 xc7s50csga324 \
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xc7k160tffg676 \
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xc7k325tffg676 xc7k325tffg900 \
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@ -0,0 +1,11 @@
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
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set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
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set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
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