xc7vx330tffg1157: Allow to build and provide spiOverJtag_xc7vx330tffg1157.bit

spiOverJtag/Makefile

@@ -15,6 +15,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901 \
 	xcku3p-ffva676 \
+	xc7vx330tffg1157 \
 	xcku5p-ffvb676 \
 	xcvu9p-flga2104 xcvu37p-fsvh2892
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

spiOverJtag/build.py

@@ -35,6 +35,9 @@ elif subpart[0:2] == '5c':
 elif subpart == "xc7a":
     family = "Artix"
     tool = "vivado"
+elif subpart == "xc7v":
+    family = "Virtex 7"
+    tool = "vivado"
 elif subpart == "xc7k":
     device_size = int(part.split('k')[1].split('t')[0])
     if device_size <= 160:
@@ -100,6 +103,7 @@ if tool in ["ise", "vivado"]:
         "xc7k325tffg676"   : "xc7k_ffg676",
         "xc7k325tffg900"   : "xc7k_ffg900",
         "xc7k420tffg901"   : "xc7k_ffg901",
+        "xc7vx330tffg1157" : "xc7v_ffg1157",
         "xc7s25csga225"    : "xc7s_csga225",
         "xc7s25csga324"    : "xc7s_csga324",
         "xc7s50csga324"    : "xc7s_csga324",

spiOverJtag/constr_xc7v_ffg1157.ucf

@@ -0,0 +1,5 @@
+NET "csn"       LOC = AL33 | IOSTANDARD = LVCMOS18;
+NET "sdi_dq0"   LOC = AN33 | IOSTANDARD = LVCMOS18;
+NET "sdo_dq1"   LOC = AN34 | IOSTANDARD = LVCMOS18;
+NET "wpn_dq2"   LOC = AK34 | IOSTANDARD = LVCMOS18;
+NET "hldn_dq3"  LOC = AL34 | IOSTANDARD = LVCMOS18;

spiOverJtag/constr_xc7v_ffg1157.xdc

@@ -0,0 +1,11 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+
+set_property -dict {PACKAGE_PIN AL33 IOSTANDARD LVCMOS18} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN AN33 IOSTANDARD LVCMOS18} [get_ports {sdi_dq0}]
+set_property -dict {PACKAGE_PIN AN34 IOSTANDARD LVCMOS18} [get_ports {sdo_dq1}]
+set_property -dict {PACKAGE_PIN AK34 IOSTANDARD LVCMOS18} [get_ports {wpn_dq2}]
+set_property -dict {PACKAGE_PIN AL34 IOSTANDARD LVCMOS18} [get_ports {hldn_dq3}]