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Merge pull request #123 from UweBonnes/xc95_wait 

xilinx: Adapt wait times with JTAG frequency.
This commit is contained in:
Gwenhael Goavec-Merou 2021-10-03 17:46:52 +02:00 committed by GitHub
parent c165154317 f6dfee2db0
commit 16598ceacd
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 7 deletions
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10
src/xilinx.cpp
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@ -448,7 +448,7 @@ void Xilinx::flow_enable()
void Xilinx::flow_disable()
{
_jtag->shiftIR(XC95_ISC_DISABLE, 8);
usleep(100);
_jtag->toggleClk((_jtag->getClkFreq() * 100) / 1000000);
_jtag->shiftIR(BYPASS, 8);
_jtag->toggleClk(1);
}
@ -461,7 +461,7 @@ bool Xilinx::flow_erase()
_jtag->shiftIR(XC95_ISC_ERASE, 8);
_jtag->shiftDR(xfer_buf, NULL, 18);
_jtag->toggleClk(2000000);
_jtag->toggleClk((_jtag->getClkFreq() * 400) / 1000);
_jtag->shiftDR(NULL, xfer_buf, 18);
if ((xfer_buf[0] & 0x03) != 0x01) {
printError("FAIL");
@ -500,10 +500,6 @@ bool Xilinx::flow_program()
}
printSuccess("DONE");
/* limit JTAG clock frequency to 1MHz */
if (_jtag->getClkFreq() > 1e6)
_jtag->setClkFreq(1e6);
/* enable ISC */
flow_enable();
@ -545,7 +541,7 @@ bool Xilinx::flow_program()
_jtag->shiftIR(XC95_ISC_PROGRAM, 8);
_jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
_jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
_jtag->toggleClk(50000);
_jtag->toggleClk((_jtag->getClkFreq() * 50) / 1000);
_jtag->shiftDR(NULL, rd_buf, 8 * (_xc95_line_len + 2) + 2);
if ((rd_buf[0] & 0x03) == 0x01)
break;