deploy: b4831e0a64
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@ -782,329 +782,336 @@ openFPGALoader<span class="w"> </span>-b<span class="w"> </span>arty<span class=
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<td><p>NT</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>spartanEdgeAccelBoard</p></td>
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<tr class="row-even"><td><p>sp701</p></td>
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<td><p><a class="reference external" href="https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/sp701.html">Xilinx SP701</a></p></td>
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<td><p>Spartan 7 xc7s100-2-fgga676</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>spartanEdgeAccelBoard</p></td>
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<td><p><a class="reference external" href="http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board">SeeedStudio Spartan Edge Accelerator Board</a></p></td>
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<td><p>Spartan7 xc7s15ftgb196</p></td>
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<td><p>OK</p></td>
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<td><p>NA</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>SPEC45</p></td>
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<tr class="row-even"><td><p>SPEC45</p></td>
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<td><p><a class="reference external" href="https://ohwr.org/project/spec150/wikis/home">CERN Simple PCIe FMC carrier SPEC</a></p></td>
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<td><p>Spartan6 xc6slx45Tfgg484</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>SPEC150</p></td>
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<tr class="row-odd"><td><p>SPEC150</p></td>
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<td><p><a class="reference external" href="https://ohwr.org/project/spec150/wikis/home">CERN Simple PCIe FMC carrier SPEC</a></p></td>
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<td><p>Spartan6 xc6slx150Tfgg484</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>stlv7325</p></td>
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<tr class="row-even"><td><p>stlv7325</p></td>
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<td><p><a class="reference external" href="https://www.aliexpress.com/item/1005001275162791.html">Sitlinv STLV7325 Board</a></p></td>
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<td><p>Kintex xc7k325tffg676</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tangconsole</p></td>
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<tr class="row-odd"><td><p>tangconsole</p></td>
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<td><p><a class="reference external" href="https://wiki.sipeed.com/hardware/en/tang/tang-console/mega-console.html">Sipeed Tang Console (dock board for Tang Mega 60k or 138k SOM)</a></p></td>
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<td><p>Gowin Arora V GW5AT-60 / GW5AT-138</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>tangnano</p></td>
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<tr class="row-even"><td><p>tangnano</p></td>
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<td><p><a class="reference external" href="https://tangnano.sipeed.com/en/">Sipeed Tang Nano</a></p></td>
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<td><p>littleBee GW1N-1</p></td>
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<td><p>OK</p></td>
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<td></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tangnano1k</p></td>
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<tr class="row-odd"><td><p>tangnano1k</p></td>
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<td><p><a class="reference external" href="https://tangnano.sipeed.com/en/">Sipeed Tang Nano 1K</a></p></td>
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<td><p>littleBee GW1NZ-1</p></td>
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<td><p>OK</p></td>
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<td><p>IF</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>tangnano4k</p></td>
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<tr class="row-even"><td><p>tangnano4k</p></td>
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<td><p><a class="reference external" href="https://tangnano.sipeed.com/en/">Sipeed Tang Nano 4K</a></p></td>
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<td><p>littleBee GW1NSR-4C</p></td>
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<td><p>OK</p></td>
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<td><p>IF/EF</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tangnano9k</p></td>
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<tr class="row-odd"><td><p>tangnano9k</p></td>
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<td><p><a class="reference external" href="https://tangnano.sipeed.com/en/">Sipeed Tang Nano 9K</a></p></td>
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<td><p>littleBee GW1NR-9C</p></td>
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<td><p>OK</p></td>
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<td><p>IF/EF</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>tangnano20k</p></td>
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<tr class="row-even"><td><p>tangnano20k</p></td>
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<td><p><a class="reference external" href="https://wiki.sipeed.com/nano20k">Sipeed Tang Nano 20k</a></p></td>
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<td><p>Gowin Arora GW2A(R)-18(C)</p></td>
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<td><p>OK</p></td>
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<td><p>EF</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tangprimer20k</p></td>
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<tr class="row-odd"><td><p>tangprimer20k</p></td>
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<td><p><a class="reference external" href="https://wiki.sipeed.com/en/primer20k">Sipeed Tang Primer 20k</a></p></td>
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<td><p>Gowin Arora GW2A(R)-18(C)</p></td>
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<td><p>OK</p></td>
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<td><p>EF</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>tangprimer25k</p></td>
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<tr class="row-even"><td><p>tangprimer25k</p></td>
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<td><p><a class="reference external" href="https://wiki.sipeed.com/hardware/zh/tang/tang-primer-25k/primer-25k.html">Sipeed Tang Primer 25k</a></p></td>
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<td><p>Gowin Arora V GW5A-25A (GW5A-LV25MG121)</p></td>
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<td><p>OK</p></td>
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<td><p>TBD</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tangmega138k</p></td>
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<tr class="row-odd"><td><p>tangmega138k</p></td>
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<td><p><a class="reference external" href="https://wiki.sipeed.com/hardware/zh/tang/tang-mega-138k/mega-138k.html">Sipeed Tang Mega 138k</a></p></td>
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<td><p>Gowin Arora V GW5AST-138B (GW5AST-LV138FPG676A)</p></td>
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<td><p>OK</p></td>
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<td><p>TBD</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>te0712_8</p></td>
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<tr class="row-even"><td><p>te0712_8</p></td>
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<td><p><a class="reference external" href="https://shop.trenz-electronic.de/en/TE0712-03-81I36-A-FPGA-Module-with-AMD-Artix-7-XC7A200T-1FBG484I-1-GByte-DDR3-4-x-5-cm">Trenz Electronic TE0712 FPGA-Module mit AMD Artix™ 7(TE0712)</a></p></td>
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<td><p>XC7A200TFBG484</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tec0117</p></td>
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<tr class="row-odd"><td><p>tec0117</p></td>
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<td><p><a class="reference external" href="https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM">Trenz Gowin LittleBee (TEC0117)</a></p></td>
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<td><p>littleBee GW1NR-9</p></td>
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<td><p>OK</p></td>
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<td><p>IF</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>trion_t20_bga256_jtag</p></td>
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<tr class="row-even"><td><p>trion_t20_bga256_jtag</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont20.html">Efinix Trion T20 BGA256 Dev Kit</a></p></td>
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<td><p>Trion T20BGA256</p></td>
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<td><p>OK</p></td>
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<td><p>NT</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>tec0330</p></td>
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<tr class="row-odd"><td><p>tec0330</p></td>
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<td><p><a class="reference external" href="https://shop.trenz-electronic.de//TEC0330-05-PCIe-FMC-Carrier-with-Xilinx-Virtex-7-FPGA-8-Lane-PCIe-GEN2-SODIMM-SDRAM">PCIe FMC Carrier with Xilinx Virtex-7 FPGA (TEC0330)</a></p></td>
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<td><p>XC7VX330T-2FFG1157C</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>trion_t120_bga576</p></td>
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<tr class="row-even"><td><p>trion_t120_bga576</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont120bga576.html">Efinix Trion T120 BGA576 Dev Kit (SPI mode)</a></p></td>
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<td><p>Trion T120BGA576</p></td>
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<td><p>NA</p></td>
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<td><p>AS</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>trion_t120_bga576_jtag</p></td>
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<tr class="row-odd"><td><p>trion_t120_bga576_jtag</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont120bga576.html">Efinix Trion T120 BGA576 Dev Kit (JTAG mode)</a></p></td>
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<td><p>Trion T120BGA576</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>trion_ti60_f225</p></td>
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<tr class="row-even"><td><p>trion_ti60_f225</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti60f225.html">Efinix Titanium F225 Dev Kit (SPI mode)</a></p></td>
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<td><p>Titanium Ti60F225</p></td>
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<td><p>NA</p></td>
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<td><p>AS</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>trion_ti60_f225_jtag</p></td>
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<tr class="row-odd"><td><p>trion_ti60_f225_jtag</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti60f225.html">Efinix Titanium F225 Dev Kit (JTAG mode)</a></p></td>
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<td><p>Titanium Ti60F225</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>ulx3s</p></td>
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<tr class="row-even"><td><p>ulx3s</p></td>
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<td><p><a class="reference external" href="https://radiona.org/ulx3s/">Radiona ULX3S</a></p></td>
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<td><p>ECP5 LFE5U</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-12f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-12F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-25f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-25F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-45f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-45F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-85f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-85F ➚</span></a></p></td>
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</tr>
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<tr class="row-even"><td><p>ulx3s_dfu</p></td>
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<tr class="row-odd"><td><p>ulx3s_dfu</p></td>
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<td><p><a class="reference external" href="https://github.com/emard/had2019-playground">Radiona ULX3S DFU mode</a></p></td>
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<td><p>ECP5 LFE5U</p></td>
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<td><p>NA</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>ulx4m_dfu</p></td>
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<tr class="row-even"><td><p>ulx4m_dfu</p></td>
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<td><p><a class="reference external" href="https://github.com/intergalaktik/ulx4m-ls">Radiona ULX4M LD/LS DFU mode</a></p></td>
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<td><p>ECP5 LFE5U</p></td>
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<td><p>NA</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>vec_v6</p></td>
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<tr class="row-odd"><td><p>vec_v6</p></td>
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<td><p><a class="reference external" href="https://vmm-srs.docs.cern.ch/">Xilinx VCU118</a></p></td>
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<td><p>xc6vlx130tff784</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>vc709</p></td>
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<tr class="row-even"><td><p>vc709</p></td>
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<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html">AMD Virtex-7 FPGA VC709 Connectivity Kit</a></p></td>
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<td><p>Virtex7 xc7vx690tffg1761</p></td>
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<td><p>OK</p></td>
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<td><p>NA</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>vcu108</p></td>
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<tr class="row-odd"><td><p>vcu108</p></td>
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<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu108.html">Xilinx VCU108</a></p></td>
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<td><p>Virtex UltraScale xcvu095-ffva2104</p></td>
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<td><p>OK</p></td>
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<td><p>TBD</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>vcu118</p></td>
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<tr class="row-even"><td><p>vcu118</p></td>
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<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu118.html">Xilinx VCU118</a></p></td>
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<td><p>Virtex UltraScale+ xcvu9p-flga2104</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>vcu128</p></td>
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<tr class="row-odd"><td><p>vcu128</p></td>
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<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu128.html">Xilinx VCU128</a></p></td>
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<td><p>Virtex UltraScale+ xcvu37p-fsvh2892</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>vcu1525</p></td>
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<tr class="row-even"><td><p>vcu1525</p></td>
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<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html">AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit</a></p></td>
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<td><p>Virtex UltraScale+ xcvu9p-fsgd2104</p></td>
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<td><p>OK</p></td>
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<td><p>NT</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>xtrx</p></td>
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<tr class="row-odd"><td><p>xtrx</p></td>
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<td><p><a class="reference external" href="https://www.crowdsupply.com/fairwaves/xtrx">FairWaves XTRXPro</a></p></td>
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<td><p>Artix xc7a50tcpg236</p></td>
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<td><p>OK</p></td>
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<td><p>OK</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>xyloni_spi</p></td>
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<tr class="row-even"><td><p>xyloni_spi</p></td>
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<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-xyloni.html">Efinix Xyloni</a></p></td>
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<td><p>Trion T8F81</p></td>
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<td><p>NA</p></td>
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<td><p>AS</p></td>
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<td></td>
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</tr>
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||||
<tr class="row-even"><td><p>usrpx300</p></td>
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<tr class="row-odd"><td><p>usrpx300</p></td>
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<td><p><a class="reference external" href="https://www.ettus.com/all-products/x300-kit/">Ettus Research USRP X300</a></p></td>
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<td><p>Kintex xc7k325tffg900</p></td>
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<td><p>OK</p></td>
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<td><p>NA</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>usrpx310</p></td>
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<tr class="row-even"><td><p>usrpx310</p></td>
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<td><p><a class="reference external" href="https://www.ettus.com/all-products/x310-kit/">Ettus Research USRP X300</a></p></td>
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<td><p>Kintex xc7k410tffg900</p></td>
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<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>xmf3</p></td>
|
||||
<tr class="row-odd"><td><p>xmf3</p></td>
|
||||
<td><p><a class="reference external" href="https://pldkit.com/xilinx/xmf3">PLDkit XMF3</a></p></td>
|
||||
<td><p>Xilinx xc3s200ft256, xcf01s</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>ypcb003381p1</p></td>
|
||||
<tr class="row-even"><td><p>ypcb003381p1</p></td>
|
||||
<td><p><a class="reference external" href="https://www.tiferking.cn/index.php/2024/12/19/650/">YPCB-00338-1P1 Kintex-7 Accelerator Card</a></p></td>
|
||||
<td><p>Kintex7 xc7k480tffg1156</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>OK. BPI parallel NOR flash (MT28GU512AAA1EGC)</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>zc702</p></td>
|
||||
<tr class="row-odd"><td><p>zc702</p></td>
|
||||
<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html">Xilinx ZC702</a></p></td>
|
||||
<td><p>zynq7000 xc7z020clg484</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>zc706</p></td>
|
||||
<tr class="row-even"><td><p>zc706</p></td>
|
||||
<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html">Xilinx ZC706</a></p></td>
|
||||
<td><p>zynq7000 xc7z045ffg900</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-zc706" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ZC706 ➚</span></a></p></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>zcu102</p></td>
|
||||
<tr class="row-odd"><td><p>zcu102</p></td>
|
||||
<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html">Xilinx ZCU102</a></p></td>
|
||||
<td><p>zynqMPSoC XCZU9EG</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>zcu106</p></td>
|
||||
<tr class="row-even"><td><p>zcu106</p></td>
|
||||
<td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/zcu106.html">Xilinx ZCU106</a></p></td>
|
||||
<td><p>zynqMPSoC XCZU7EV</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>zedboard</p></td>
|
||||
<tr class="row-odd"><td><p>zedboard</p></td>
|
||||
<td><p><a class="reference external" href="https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/">Avnet ZedBoard</a></p></td>
|
||||
<td><p>zynq7000 xc7z020clg484</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-zedboard" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ZedBoard ➚</span></a></p></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>zybo_z7_10</p></td>
|
||||
<tr class="row-even"><td><p>zybo_z7_10</p></td>
|
||||
<td><p><a class="reference external" href="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start">Digilent Zybo Z7-10</a></p></td>
|
||||
<td><p>zynq7000 xc7z010clg400</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>zybo_z7_20</p></td>
|
||||
<tr class="row-odd"><td><p>zybo_z7_20</p></td>
|
||||
<td><p><a class="reference external" href="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start">Digilent Zybo Z7-20</a></p></td>
|
||||
<td><p>zynq7000 xc7z020clg400</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>VMM3</p></td>
|
||||
<tr class="row-even"><td><p>VMM3</p></td>
|
||||
<td><p><a class="reference external" href="https://vmm-srs.docs.cern.ch/">CERN board with VMM3</a></p></td>
|
||||
<td><p>xc7s50csga324?</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>efinix_jtag_ft2232</p></td>
|
||||
<tr class="row-odd"><td><p>efinix_jtag_ft2232</p></td>
|
||||
<td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti180j484.html">Efinix FT2232 development boards with JTAG on port 2 (Ti180J484 EVK, etc)</a></p></td>
|
||||
<td><p>Titanium Ti180J484 (and others)</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-odd"><td><p>step-max10_v1</p></td>
|
||||
<tr class="row-even"><td><p>step-max10_v1</p></td>
|
||||
<td><p><a class="reference external" href="https://wiki.stepfpga.com/step-max10">STEP MAX10 V1</a></p></td>
|
||||
<td><p>Altera 10M02SCM153C8G</p></td>
|
||||
<td><p>OK</p></td>
|
||||
<td><p>NA</p></td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr class="row-even"><td><p>step-mxo2_v2</p></td>
|
||||
<tr class="row-odd"><td><p>step-mxo2_v2</p></td>
|
||||
<td><p><a class="reference external" href="https://wiki.stepfpga.com/xo2-4000hc">STEP MXO2 V2</a></p></td>
|
||||
<td><p>Lattice LCMXO2-4000HC-4MG132CC</p></td>
|
||||
<td><p>OK</p></td>
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue