Merge pull request #260 from jeanbie0/jetson-nano-gpio
Add cable jetson-nano-gpio
This commit is contained in:
Gwenhael Goavec-Merou
GitHub
commit
106cdecc14
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@ -218,9 +218,16 @@ if (ENABLE_LIBGPIOD)
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message("libgpiod support enabled")
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endif(ENABLE_LIBGPIOD)
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if (ENABLE_UDEV OR ENABLE_LIBGPIOD)
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if (ENABLE_JETSONNANOGPIO)
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add_definitions(-DENABLE_JETSONNANOGPIO=1)
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target_sources(openFPGALoader PRIVATE src/jetsonNanoJtagBitbang.cpp)
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list (APPEND OPENFPGALOADER_HEADERS src/jetsonNanoJtagBitbang.hpp)
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message("Jetson Nano GPIO support enabled")
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endif(ENABLE_JETSONNANOGPIO)
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if (ENABLE_UDEV OR ENABLE_LIBGPIOD OR ENABLE_JETSONNANOGPIO)
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add_definitions(-DUSE_DEVICE_ARG)
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endif(ENABLE_UDEV OR ENABLE_LIBGPIOD)
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endif(ENABLE_UDEV OR ENABLE_LIBGPIOD OR ENABLE_JETSONNANOGPIO)
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if (BUILD_STATIC)
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set_target_properties(openFPGALoader PROPERTIES LINK_SEARCH_END_STATIC 1)
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@ -257,3 +257,9 @@ libgpiod:
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- Name: Bitbang GPIO
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Description: Bitbang GPIO pins on Linux host.
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URL: https://github.com/brgl/libgpiod
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jetson-nano-gpio:
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- Name: Bitbang GPIO
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Description: Bitbang GPIO pins on Jetson Nano Linux host. Use /dev/mem to have a faster clock.
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URL: https://github.com/jwatte/jetson-gpio-example
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@ -24,6 +24,7 @@ enum communication_type {
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MODE_DFU, /*! DFU based probe */
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MODE_XVC_CLIENT, /*! Xilinx Virtual Cable client */
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MODE_LIBGPIOD_BITBANG, /*! Bitbang gpio pins */
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MODE_JETSONNANO_BITBANG, /*! Bitbang gpio pins */
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};
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/*!
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@ -115,6 +116,9 @@ static std::map <std::string, cable_t> cable_list = {
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#ifdef ENABLE_LIBGPIOD
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{"libgpiod", CABLE_DEF(MODE_LIBGPIOD_BITBANG, 0, 0x0000 )},
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#endif
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#ifdef ENABLE_JETSONNANOGPIO
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{"jetson-nano-gpio", {MODE_JETSONNANO_BITBANG, {}}},
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#endif
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};
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#endif // SRC_CABLE_HPP_
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@ -0,0 +1,269 @@
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2020-2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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* Copyright (C) 2022 Jean Biemar <jb@altaneos.com>
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*
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* Jetson nano bitbang driver added by Jean Biemar <jb@altaneos.com> in 2022
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*/
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#include "jetsonNanoJtagBitbang.hpp"
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#include <stdio.h>
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#include <string.h>
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#include <iostream>
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#include <map>
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#include <vector>
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#include <string>
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#include <stdexcept>
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#include <unistd.h>
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#include <sys/fcntl.h>
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#include <sys/mman.h>
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#include "display.hpp"
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#define DEBUG 1
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#ifdef DEBUG
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#define display(...) \
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do { \
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if (_verbose) fprintf(stdout, __VA_ARGS__); \
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}while(0)
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#else
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#define display(...) do {}while(0)
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#endif
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/* Tegra X1 SoC Technical Reference Manual, version 1.3
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*
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* See Chapter 9 "Multi-Purpose I/O Pins", section 9.13 "GPIO Registers"
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* (table 32: GPIO Register Address Map)
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*
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* The GPIO hardware shares PinMux with up to 4 Special Function I/O per
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* pin, and only one of those five functions (SFIO plus GPIO) can be routed to
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* a pin at a time, using the PixMux.
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*
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* In turn, the PinMux outputs signals to Pads using Pad Control Groups. Pad
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* control groups control things like "drive strength" and "slew rate," and
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* need to be reset after deep sleep. Also, different pads have different
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* voltage tolerance. Pads marked "CZ" can be configured to be 3.3V tolerant
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* and driving; and pads marked "DD" can be 3.3V tolerant when in open-drain
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* mode (only.)
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*
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* The CNF register selects GPIO or SFIO, so setting it to 1 forces the GPIO
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* function. This is convenient for those who have a different pinmux at boot.
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*/
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#define GPIO_SET_BIT(REG, BIT) REG |= 1UL << BIT
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#define GPIO_CLEAR_BIT(REG, BIT) REG &= ~(1UL << BIT)
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JetsonNanoJtagBitbang::JetsonNanoJtagBitbang(
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const jtag_pins_conf_t *pin_conf,
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const std::string &dev, __attribute__((unused)) uint32_t clkHZ,
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uint8_t verbose)
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{
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uint32_t tms_port_reg, tck_port_reg, tdi_port_reg, tdo_port_reg;
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_verbose = verbose;
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_tck_pin = pin_conf->tck_pin;
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_tms_pin = pin_conf->tms_pin;
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_tdi_pin = pin_conf->tdi_pin;
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_tdo_pin = pin_conf->tdo_pin;
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display("Jetson Nano jtag bitbang driver, tck_pin=%d, tms_pin=%d, tdi_pin=%d, tdo_pin=%d\n",
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_tck_pin, _tms_pin, _tdi_pin, _tdo_pin);
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/* Validate pins */
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int pins[] = {_tck_pin, _tms_pin, _tdi_pin, _tdo_pin};
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for (uint32_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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if (pins[i] < 0 || pins[i] >= 1000) {
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display("Pin %d is outside of valid range\n", pins[i]);
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throw std::runtime_error("A pin is outside of valid range\n");
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}
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for (uint32_t j = i + 1; j < sizeof(pins) / sizeof(pins[0]); j++) {
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if (pins[i] == pins[j]) {
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display("Two or more pins are assigned to the same pin number %d\n", pins[i]);
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throw std::runtime_error("Two or more pins are assigned to the same pin number\n");
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}
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}
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}
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/* Get ports */
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tms_port_reg = GPIO_PORT_BASE + ((_tms_pin/8)/GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_LARGE_OFFSET) + ((_tms_pin/8)%GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_SHORT_OFFSET);
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tck_port_reg = GPIO_PORT_BASE + ((_tck_pin/8)/GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_LARGE_OFFSET) + ((_tck_pin/8)%GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_SHORT_OFFSET);
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tdi_port_reg = GPIO_PORT_BASE + ((_tdi_pin/8)/GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_LARGE_OFFSET) + ((_tdi_pin/8)%GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_SHORT_OFFSET);
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tdo_port_reg = GPIO_PORT_BASE + ((_tdo_pin/8)/GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_LARGE_OFFSET) + ((_tdo_pin/8)%GPIO_PORT_SHORT_OFFSET_SIZE*GPIO_PORT_SHORT_OFFSET);
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/* Get pin */
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_tms_pin %= 8;
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_tck_pin %= 8;
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_tdi_pin %= 8;
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_tdo_pin %= 8;
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display("reg:pin details: TMS %x:%i, TCK %x:%i, TDI %x:%i, TDO %x:%i\n", tms_port_reg, _tms_pin, tck_port_reg, _tck_pin, tdi_port_reg, _tdi_pin, tdo_port_reg, _tdo_pin);
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_curr_tdi = 0;
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_curr_tck = 0;
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_curr_tms = 1;
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// FIXME: I'm unsure how this value should be set.
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// Maybe experiment, or think through what it should be.
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_clkHZ = 5000000;
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// read physical memory (needs root)
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int fd = open("/dev/mem", O_RDWR | O_SYNC);
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if (fd < 0) {
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display("Can't open /dev/mem. Error %x\n", errno);
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throw std::runtime_error("No access to /dev/mem\n");
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}
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// map a particular physical address into our address space
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int pagesize = getpagesize();
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int pagemask = pagesize-1;
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// This page will actually contain all the GPIO controllers, because they are co-located
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void *base = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, ((tms_port_reg | tck_port_reg | tdi_port_reg | tdo_port_reg) & ~pagemask));
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if (base == NULL) {
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display("mmap return error\n");
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throw std::runtime_error("mmap error\n");
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}
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_tms_port = (gpio_t volatile *)((char *)base + (tms_port_reg & pagemask));
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_tck_port = (gpio_t volatile *)((char *)base + (tck_port_reg & pagemask));
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_tdi_port = (gpio_t volatile *)((char *)base + (tdi_port_reg & pagemask));
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_tdo_port = (gpio_t volatile *)((char *)base + (tdo_port_reg & pagemask));
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// for _tms_port : GPIO OUT
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GPIO_SET_BIT(_tms_port->CNF, _tms_pin);
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GPIO_SET_BIT(_tms_port->OE, _tms_pin);
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GPIO_SET_BIT(_tms_port->OUT, _tms_pin);
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// for _tck_port : GPIO OUT
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GPIO_SET_BIT(_tck_port->CNF, _tck_pin);
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GPIO_SET_BIT(_tck_port->OE, _tck_pin);
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GPIO_CLEAR_BIT(_tck_port->OUT, _tck_pin);
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// for _tdi_port : GPIO OUT
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GPIO_SET_BIT(_tdi_port->CNF, _tdi_pin);
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GPIO_SET_BIT(_tdi_port->OE, _tdi_pin);
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GPIO_CLEAR_BIT(_tdi_port->OUT, _tdi_pin);
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// for _tdo_port : GPIO IN
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GPIO_SET_BIT(_tdo_port->CNF, _tdo_pin);
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GPIO_CLEAR_BIT(_tdo_port->OE , _tdo_pin);
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GPIO_CLEAR_BIT(_tdo_port->IN, _tdo_pin);
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}
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JetsonNanoJtagBitbang::~JetsonNanoJtagBitbang()
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{
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GPIO_CLEAR_BIT(_tms_port->OE, _tms_pin);
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GPIO_CLEAR_BIT(_tck_port->OE, _tck_pin);
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GPIO_CLEAR_BIT(_tdi_port->OE, _tdi_pin);
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GPIO_CLEAR_BIT(_tms_port->CNF, _tms_pin);
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GPIO_CLEAR_BIT(_tck_port->CNF, _tck_pin);
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GPIO_CLEAR_BIT(_tdi_port->CNF, _tdi_pin);
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GPIO_CLEAR_BIT(_tdo_port->CNF, _tdo_pin);
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}
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int JetsonNanoJtagBitbang::update_pins(int tck, int tms, int tdi)
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{
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if (tdi != _curr_tdi) {
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if(tdi)
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GPIO_SET_BIT(_tdi_port->OUT, _tdi_pin);
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else
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GPIO_CLEAR_BIT(_tdi_port->OUT, _tdi_pin);
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}
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if (tms != _curr_tms) {
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if(tms)
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GPIO_SET_BIT(_tms_port->OUT, _tms_pin);
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else
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GPIO_CLEAR_BIT(_tms_port->OUT, _tms_pin);
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}
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if (tck != _curr_tck) {
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if(tck)
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GPIO_SET_BIT(_tck_port->OUT, _tck_pin);
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else
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GPIO_CLEAR_BIT(_tck_port->OUT, _tck_pin);
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}
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_curr_tdi = tdi;
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_curr_tms = tms;
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_curr_tck = tck;
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return 0;
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}
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int JetsonNanoJtagBitbang::read_tdo()
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{
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return (_tdo_port->IN>>_tdo_pin) & 0x01;
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}
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int JetsonNanoJtagBitbang::setClkFreq(__attribute__((unused)) uint32_t clkHZ)
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{
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// FIXME: The assumption is that calling the gpiod_line_set_value
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// routine will limit the clock frequency to lower than what is specified.
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// This needs to be verified, and possibly artificial delays should be added.
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return 0;
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}
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int JetsonNanoJtagBitbang::writeTMS(uint8_t *tms_buf, uint32_t len,
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__attribute__((unused)) bool flush_buffer)
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{
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int tms;
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for (uint32_t i = 0; i < len; i++) {
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tms = ((tms_buf[i >> 3] & (1 << (i & 7))) ? 1 : 0);
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update_pins(0, tms, 0);
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update_pins(1, tms, 0);
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}
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update_pins(0, tms, 0);
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return len;
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}
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int JetsonNanoJtagBitbang::writeTDI(uint8_t *tx, uint8_t *rx, uint32_t len, bool end)
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{
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int tms = _curr_tms;
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int tdi = _curr_tdi;
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if (rx)
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memset(rx, 0, len / 8);
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for (uint32_t i = 0; i < len; i++) {
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if (end && (i == len - 1))
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tms = 1;
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if (tx)
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tdi = (tx[i >> 3] & (1 << (i & 7))) ? 1 : 0;
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update_pins(0, tms, tdi);
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update_pins(1, tms, tdi);
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if (rx) {
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if (read_tdo() > 0)
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rx[i >> 3] |= 1 << (i & 7);
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}
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}
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update_pins(0, tms, tdi);
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return len;
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}
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int JetsonNanoJtagBitbang::toggleClk(uint8_t tms, uint8_t tdi, uint32_t clk_len)
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{
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for (uint32_t i = 0; i < clk_len; i++) {
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update_pins(0, tms, tdi);
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update_pins(1, tms, tdi);
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}
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update_pins(0, tms, tdi);
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return clk_len;
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}
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@ -0,0 +1,105 @@
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2020-2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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* Copyright (C) 2022 Jean Biemar <jb@altaneos.com>
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*
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* Jetson nano bitbang driver added by Jean Biemar <jb@altaneos.com> in 2022
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*/
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#ifndef JETSONNANOBITBANG_H
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#define JETSONNANOBITBANG_H
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#include <string>
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#include "board.hpp"
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#include "jtagInterface.hpp"
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/* Tegra X1 SoC Technical Reference Manual, version 1.3
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*
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* See Chapter 9 "Multi-Purpose I/O Pins", section 9.13 "GPIO Registers"
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* (table 32: GPIO Register Address Map)
|
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*
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* The GPIO hardware shares PinMux with up to 4 Special Function I/O per
|
||||
* pin, and only one of those five functions (SFIO plus GPIO) can be routed to
|
||||
* a pin at a time, using the PixMux.
|
||||
*
|
||||
* In turn, the PinMux outputs signals to Pads using Pad Control Groups. Pad
|
||||
* control groups control things like "drive strength" and "slew rate," and
|
||||
* need to be reset after deep sleep. Also, different pads have different
|
||||
* voltage tolerance. Pads marked "CZ" can be configured to be 3.3V tolerant
|
||||
* and driving; and pads marked "DD" can be 3.3V tolerant when in open-drain
|
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* mode (only.)
|
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*
|
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* The CNF register selects GPIO or SFIO, so setting it to 1 forces the GPIO
|
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* function. This is convenient for those who have a different pinmux at boot.
|
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*/
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#define GPIO_PORT_BASE 0x6000d000 // Port A
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#define GPIO_PORT_MAX 0x6000d708 // Port EE
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#define GPIO_PORT_SHORT_OFFSET_SIZE 4
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#define GPIO_PORT_SHORT_OFFSET 0x00000004
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#define GPIO_PORT_LARGE_OFFSET 0x00000100
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/*!
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* \file JetsonNanoJtagBitbang.hpp
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* \class JetsonNanoJtagBitbang
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* \brief concrete class between jtag implementation and gpio bitbang
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* \author Jean Biemar
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*/
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class JetsonNanoJtagBitbang : public JtagInterface {
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public:
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JetsonNanoJtagBitbang(const jtag_pins_conf_t *pin_conf,
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const std::string &dev, uint32_t clkHZ, uint8_t verbose);
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virtual ~JetsonNanoJtagBitbang();
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int setClkFreq(uint32_t clkHZ) override;
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int writeTMS(uint8_t *tms_buf, uint32_t len, bool flush_buffer) override;
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int writeTDI(uint8_t *tx, uint8_t *rx, uint32_t len, bool end) override;
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int toggleClk(uint8_t tms, uint8_t tdo, uint32_t clk_len) override;
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int get_buffer_size() override { return 0; }
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bool isFull() override { return false; }
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int flush() override { return 0; }
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private:
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// layout based on the definitions above
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// Each GPIO controller has four ports, each port controls 8 pins, each
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// register is interleaved for the four ports, so
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// REGX: port0, port1, port2, port3
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// REGY: port0, port1, port2, port3
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typedef struct {
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uint32_t CNF;
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uint32_t _padding1[3];
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uint32_t OE;
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uint32_t _padding2[3];
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uint32_t OUT;
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uint32_t _padding3[3];
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uint32_t IN;
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uint32_t _padding4[3];
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uint32_t INT_STA;
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uint32_t _padding5[3];
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uint32_t INT_ENB;
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uint32_t _padding6[3];
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uint32_t INT_LVL;
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uint32_t _padding7[3];
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uint32_t INT_CLR;
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uint32_t _padding8[3];
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} gpio_t;
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int update_pins(int tck, int tms, int tdi);
|
||||
int read_tdo();
|
||||
|
||||
bool _verbose;
|
||||
|
||||
int _tck_pin;
|
||||
int _tms_pin;
|
||||
int _tdo_pin;
|
||||
int _tdi_pin;
|
||||
|
||||
gpio_t volatile *_tms_port, *_tck_port, *_tdo_port, *_tdi_port;
|
||||
|
||||
int _curr_tms;
|
||||
int _curr_tdi;
|
||||
int _curr_tck;
|
||||
};
|
||||
#endif
|
||||
|
|
@ -20,6 +20,9 @@
|
|||
#ifdef ENABLE_LIBGPIOD
|
||||
#include "libgpiodJtagBitbang.hpp"
|
||||
#endif
|
||||
#ifdef ENABLE_JETSONNANOGPIO
|
||||
#include "jetsonNanoJtagBitbang.hpp"
|
||||
#endif
|
||||
#include "jlink.hpp"
|
||||
#ifdef ENABLE_CMSISDAP
|
||||
#include "cmsisDAP.hpp"
|
||||
|
|
@ -133,6 +136,11 @@ void Jtag::init_internal(const cable_t &cable, const string &dev, const string &
|
|||
case MODE_LIBGPIOD_BITBANG:
|
||||
_jtag = new LibgpiodJtagBitbang(pin_conf, dev, clkHZ, _verbose);
|
||||
break;
|
||||
#endif
|
||||
#ifdef ENABLE_JETSONNANOGPIO
|
||||
case MODE_JETSONNANO_BITBANG:
|
||||
_jtag = new JetsonNanoJtagBitbang(pin_conf, dev, clkHZ, _verbose);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
std::cerr << "Jtag: unknown cable type" << std::endl;
|
||||
|
|
|
|||
Loading…
Reference in New Issue