spiOverJtag: use build.py for all devices, add xc6slx45

spiOverJtag/Makefile

@@ -1,13 +1,26 @@
-VIVADO := vivado -nolog -nojournal -mode batch -source
+XILINX_PARTS := xc6slx45csg324 xc6slx100fgg484 \
-PARTS := xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a50tcpg236 xc7a75tfgg484 xc7a100tfgg484 xc7a200tsbg484 xc7s50csga324
+	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
-BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(PARTS)))
+	xc7a50tcpg236 xc7a75tfgg484 xc7a100tfgg484 xc7a200tsbg484 \
+	xc7s50csga324
+XILINX_BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
+
+ALTERA_PARTS := 10cl025256 ep4ce2217 5ce223
+ALTERA_BIT_FILES := $(addsuffix .rbf, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
+
+BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)
 
 all: $(BIT_FILES)
 
-$(BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit
+$(XILINX_BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.bit
 	cp $< $@
-tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit : xilinx_spiOverJtag.vhd
+tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
-	$(VIVADO) xilinx_spiOverJtag.tcl -tclargs $*
+	./build.py $*
+
+$(ALTERA_BIT_FILES): spiOverJtag_%.rbf: tmp_%/spiOverJtag.sof
+	quartus_cpf --option=bitstream_compression=off -c $< $@
+
+tmp_%/spiOverJtag.sof: altera_spiOverJtag.v
+	./build.py $*
 
 clean:
 	-rm -rf tmp_* *.jou *.log .Xil

spiOverJtag/build.py

@@ -39,7 +39,7 @@ elif subpart == "xc7s":
     family = "Spartan 7"
     tool = "vivado"
 elif subpart == "xc6s":
-    family = "Spartan 6"
+    family = "Spartan6"
     tool = "ise"
 else:
     print("Error: unknown device")
@@ -47,6 +47,8 @@ else:
 
 if tool in ["ise", "vivado"]:
     pkg_name = {
+        "xc6slx45csg324"   : "xc6s_csg324",
+        "xc6slx100fgg484"  : "xc6s_fgg484",
         "xc7a35tcpg236"    : "xc7a_cpg236",
         "xc7a35tcsg324"    : "xc7a_csg324",
         "xc7a35tftg256"    : "xc7a_ftg256",
@@ -59,18 +61,29 @@ if tool in ["ise", "vivado"]:
         }[part]
     if tool == "ise":
         cst_type = "UCF"
+        tool_options = {'family': family,
+                        'device': {
+                            "xc6slx45csg324": "xc6slx45",
+                            "xc6slx100fgg484": "xc6slx100"}[part],
+                        'package': {
+                            "xc6slx45csg324": "csg324",
+                            "xc6slx100fgg484": "fgg384"}[part],
+                        'speed' : -3
+                }
     else:
         cst_type = "xdc"
-    cst_file = currDir + "constr_" + pkg_name + "." + cst_type
+        tool_options = {'part': part+ '-1'}
+    cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()
     files.append({'name': currDir + 'xilinx_spiOverJtag.v',
                   'file_type': 'verilogSource'})
     files.append({'name': cst_file, 'file_type': cst_type})
-    tool_options = {'part': part+ '-1'}
 else:
     full_part = {
         "10cl025256": "10CL025YU256C8G",
         "ep4ce2217" : "EP4CE22F17C6",
-        "5ce223"    : "5CEFA2F23I7"}[part]
+        "5ce223"    : "5CEFA2F23I7",
+        "5cse423"   : "5CSEMA4U23C6",
+        "5cse623"   : "5CSEBA6U23I7"}[part]
     files.append({'name': currDir + 'altera_spiOverJtag.v',
                   'file_type': 'verilogSource'})
     files.append({'name': currDir + 'test_jtag.sdc',
@@ -93,3 +106,8 @@ edam = {'name' : "spiOverJtag",
 backend = get_edatool(tool)(edam=edam, work_root=build_dir)
 backend.configure()
 backend.build()
+
+if tool == "vivado":
+    import shutil
+    shutil.copy("tmp_" + part + "/spiOverJtag.runs/impl_1/spiOverJtag.bit",
+            "tmp_" + part);