fix up line endings and white space issues - also moved the flash sector if block into MachXO3D family - as not required for other types
This commit is contained in:
Martin Beynon
parent
b6979f54f7
commit
07752c37e2
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@ -20,14 +20,57 @@
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#include "display.hpp"
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#include "feaparser.hpp"
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/* FEAbits element defines */
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# define FEA_I2C_DG_FIL_EN (1 << 0) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
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# define FEA_FLASH_PROT_SEC_SEL (0x7 << 1) /* Flash Protection Sector Selection */
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# define FEA_MY_ASSP_EN (1 << 4) /* MY_ASSP Enabled 0=Disabled (Default), 1=Enabled */
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# define FEA_PROG_PERSIST (1 << 5) /* PROGRAMN Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_INITN_PERSIST (1 << 6) /* INITN Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_DONE_PERSIST (1 << 7) /* DONE Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_JTAG_PERSIST (1 << 8) /* JTAG Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_SSPI_PERSIST (1 << 9) /* Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_I2C_PERSIST (1 << 10) /* I²C Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_MSPI_PERSIST (1 << 11) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_BOOT_SEQ_SEL (0x07 << 12) /* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
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# define FEA_I2C_DG_RANGE_SEL (1 << 15) /* I2C deglitch filter range selection on primary I2C port2 0= 8 to 25 ns range (Default) 1= 16 to 50 ns range */
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# define FEA_VERSION_RB_PROT (1 << 16) /* Version Rollback Protection1 0= Disabled (Default) 1= Enabled (Checks if current version of bitstream is similar to the one that is goi>
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# define FEA_RESERVED_ZERO (0xffff << 17)
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/* Feature Row element defines */
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# define FEATURE_CUSTOM_ID (0xffffffff) /* 32 bits of Custom ID code */
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# define FEATURE_TRACE_ID (0xff << 0) /* 8 bits for the user programmable TraceID */
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# define FEATURE_I2C_SLAVE_ADDR (0xff << 8) /* 8 bits for the user programmable I2C Slave Address */
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# define FEATURE_DUAL_BOOT_ADDR (0xffff << 16) /* 16 bits for Dual boot address (Most significant 16- bit of address for secondary boot from external flash) */
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# define FEATURE_MASTER_RETRY_CNT (0x3 << 2) /* Master Retry Count */
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# define FEATURE_MASTER_TIMER_CNT (0x0f << 4) /* Master Timer Count */
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# define FEATURE_SLAVE_IDLE_TIMER_CNT (0x0f << 8) /* Slave Idle Timer Count */
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# define FEATURE_SFDP_CONT_FAIL (1 << 14) /* SFDP Continue on Fail */
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# define FEATURE_SFDP_EN (1 << 15) /* SFDP Enable */
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# define FEATURE_BULK_ERASE_DISABLE (1 << 16) /* No Bulk Erase */
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# define FEATURE_32BIT_SPIM (1 << 17) /* 32-bit SPIM */
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# define FEATURE_MCLK_BYPASS (1 << 18) /* MCLK Bypass */
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# define FEATURE_LSBF (1 << 19) /* LSBF */
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# define FEATURE_RX_EDGE (1 << 20)
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# define FEATURE_TX_EDGE (1 << 21)
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# define FEATURE_CPOL (1 << 22)
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# define FEATURE_CPHA (1 << 23)
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# define FEATURE_HSE_CLOCK_SEL (0x3 << 24)
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# define FEATURE_EBR_ENABLE (1 << 26)
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# define FEATURE_SSPI_AUTO (1 << 28) /* SSPI Auto */
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# define FEATURE_CPU (1 << 29) /* CPU */
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# define FEATURE_CORE_CLK_SEL (0x03 << 30) /* Core Clock Sel */
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using namespace std;
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FeaParser::FeaParser(string filename, bool verbose):
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ConfigBitstreamParser(filename, ConfigBitstreamParser::BIN_MODE, verbose),
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_feabits(0), _has_feabits(false)
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{
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for (int i=0; i < 3; i++)
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_featuresRow[i] = 0;
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for (int i=0; i < 3; i++)
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_featuresRow[i] = 0;
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}
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/* fill a vector with consecutive lines, begining with 0 or 1, until EOF
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@ -40,9 +83,9 @@ vector<string> FeaParser::readFeaFile()
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vector<string> lines;
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while (true) {
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string buffer;
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string buffer;
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std::getline(_ss, buffer, '\n');
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if (buffer.empty())
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if (buffer.empty())
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break;
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/* if '\r' is present -> drop */
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@ -50,136 +93,134 @@ vector<string> FeaParser::readFeaFile()
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buffer.pop_back();
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if (buffer.front() == '0' || buffer.front() == '1')
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lines.push_back(buffer);
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lines.push_back(buffer);
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}
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return lines;
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return lines;
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}
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void FeaParser::displayHeader()
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{
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if (_has_feabits) {
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printf("\nFeature Row: [0x");
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for(int i = 2; i >= 0; i--) {
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printf("%08x", _featuresRow[i]);
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}
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printf("]\n");
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printf("\nFeature Row: [0x");
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for (int i = 2; i >= 0; i--) {
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printf("%08x", _featuresRow[i]);
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}
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printf("]\n");
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printf("\tCore Clock Select : 0x%x\n", (_featuresRow[2] >> 30) & 0x03);
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printf("\tCPU : %d\n",
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printf("\tCore Clock Select : 0x%x\n", (_featuresRow[2] >> 30) & 0x03);
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printf("\tCPU : %d\n",
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((_featuresRow[2] & FEATURE_CPU)? 1 : 0));
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printf("\tSSPI Auto : %s\n",
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printf("\tSSPI Auto : %s\n",
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((_featuresRow[2] & FEATURE_SSPI_AUTO)?"Enabled":"Disabled"));
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printf("\tReserved Zero (1) : 0x%x\n", (_featuresRow[2] >> 27) & 0x01);
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printf("\tEBR Enable : %s\n",
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printf("\tReserved Zero (1) : 0x%x\n", (_featuresRow[2] >> 27) & 0x01);
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printf("\tEBR Enable : %s\n",
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((_featuresRow[2] & FEATURE_EBR_ENABLE)?"Yes":"No"));
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printf("\tHSE Clock Select : 0x%x\n", (_featuresRow[2] >> 24) & 0x03);
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printf("\tCPHA : %s\n",
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printf("\tHSE Clock Select : 0x%x\n", (_featuresRow[2] >> 24) & 0x03);
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printf("\tCPHA : %s\n",
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((_featuresRow[2] & FEATURE_CPHA)?"Enabled":"Disabled"));
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printf("\tCPOL : %s\n",
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printf("\tCPOL : %s\n",
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((_featuresRow[2] & FEATURE_CPOL)?"Enabled":"Disabled"));
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printf("\tTx Edge : %s\n",
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printf("\tTx Edge : %s\n",
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((_featuresRow[2] & FEATURE_TX_EDGE)?"Enabled":"Disabled"));
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printf("\tRx Edge : %s\n",
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printf("\tRx Edge : %s\n",
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((_featuresRow[2] & FEATURE_RX_EDGE)?"Enabled":"Disabled"));
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printf("\tLSBF : %s\n",
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printf("\tLSBF : %s\n",
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((_featuresRow[2] & FEATURE_LSBF)?"Enabled":"Disabled"));
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printf("\tMClock Bypass : %s\n",
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printf("\tMClock Bypass : %s\n",
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((_featuresRow[2] & FEATURE_MCLK_BYPASS)?"Enabled":"Disabled"));
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printf("\t32-bit SPIM : %s\n",
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printf("\t32-bit SPIM : %s\n",
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((_featuresRow[2] & FEATURE_32BIT_SPIM)?"Enabled":"Disabled"));
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printf("\tBulk Erase Disable : %s\n",
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printf("\tBulk Erase Disable : %s\n",
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((_featuresRow[2] & FEATURE_BULK_ERASE_DISABLE)?"Yes":"No"));
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printf("\tSFDP Enable : %s\n",
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printf("\tSFDP Enable : %s\n",
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((_featuresRow[2] & FEATURE_SFDP_EN)?"Yes":"No"));
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printf("\tSFDP Continue on Fail : %s\n",
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printf("\tSFDP Continue on Fail : %s\n",
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((_featuresRow[2] & FEATURE_SFDP_CONT_FAIL)?"Yes":"No"));
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printf("\tReserved Zero (2) : 0x%x\n", (_featuresRow[2] >> 12) & 0x03);
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printf("\tSlave Idle Timer Count: %d\n", (_featuresRow[2] >> 8) & 0x0f);
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printf("\tMaster Timer Count : %d\n", (_featuresRow[2] >> 4) & 0x0f);
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printf("\tMaster Retry Count : %d\n", (_featuresRow[2] >> 2) & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", _featuresRow[2] & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", (_featuresRow[2] >> 12) & 0x03);
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printf("\tSlave Idle Timer Count: %d\n", (_featuresRow[2] >> 8) & 0x0f);
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printf("\tMaster Timer Count : %d\n", (_featuresRow[2] >> 4) & 0x0f);
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printf("\tMaster Retry Count : %d\n", (_featuresRow[2] >> 2) & 0x03);
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printf("\tReserved Zero (2) : 0x%x\n", _featuresRow[2] & 0x03);
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printf("\tDual Boot Address : 0x%x\n", (_featuresRow[1] >> 16) & 0xffff);
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printf("\tI2C Slave Address : 0x%x\n", (_featuresRow[1] >> 8) & 0xff);
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printf("\tCustom Trace ID : 0x%x\n", _featuresRow[1] & 0xff);
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printf("\tCustom ID Code : 0x%x\n", _featuresRow[0]);
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printf("\tDual Boot Address : 0x%x\n", (_featuresRow[1] >> 16) & 0xffff);
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printf("\tI2C Slave Address : 0x%x\n", (_featuresRow[1] >> 8) & 0xff);
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printf("\tCustom Trace ID : 0x%x\n", _featuresRow[1] & 0xff);
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printf("\tCustom ID Code : 0x%x\n", _featuresRow[0]);
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printf("\nFEAbits: [0x%08x]\n", _feabits);
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printf("\tReserved Zero (16) : 0x%x\n", (_feabits >> 17) & 0xffff);
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printf("\tRollback Protection : %s\n",
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printf("\tReserved Zero (16) : 0x%x\n", (_feabits >> 17) & 0xffff);
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printf("\tRollback Protection : %s\n",
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((_feabits & FEA_VERSION_RB_PROT)?"Enabled":"Disabled"));
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printf("\tI2C Deglitch Range : %s\n",
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printf("\tI2C Deglitch Range : %s\n",
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((_feabits & FEA_I2C_DG_RANGE_SEL)?"(1) 16 to 50 ns":"(0) 8 to 25 ns"));
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int boot_mode = (_feabits >> 12) & 0x07;
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printf("\tBoot Mode : ");
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if ((_feabits & FEA_MSPI_PERSIST) == 0) {
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if (boot_mode == 0)
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printf("Dual Boot, CFG0 - CFG1\n");
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else if (boot_mode == 1)
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printf("Dual Boot, CFG1 - CFG0\n");
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else if (boot_mode == 3)
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printf("Single Boot, CFG0\n");
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else if (boot_mode == 4)
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printf("Single Boot, CFG1\n");
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else if (boot_mode == 5)
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printf("Dual Boot, Boot from former bitstream first\n");
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else if (boot_mode == 7)
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printf("Dual Boot, Boot from latter bitstream first\n");
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else if ((boot_mode & 0x03) == 2)
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printf("Dual Boot, No Boot\n");
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else
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printf("Unknown boot sequence selection");
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}
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else {
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if (boot_mode == 0)
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printf("Dual Boot, CFG0 - Ext\n");
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else if ((boot_mode & 0x03) == 1)
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printf("Single Boot, Ext\n");
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else if (boot_mode == 2)
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printf("Dual Boot, Ext - CFG0\n");
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else if ((boot_mode & 0x03) == 3)
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printf("Dual Boot, Ext - Ext\n");
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else if (boot_mode == 4)
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printf("Dual Boot, CFG1 - Ext\n");
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else if (boot_mode == 6)
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printf("Dual Boot, Ext - CFG1\n");
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else
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printf("Unknown boot sequence selection");
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}
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printf("\tMSPI Enable : %s\n",
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int boot_mode = (_feabits >> 12) & 0x07;
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printf("\tBoot Mode : ");
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if ((_feabits & FEA_MSPI_PERSIST) == 0) {
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if (boot_mode == 0)
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printf("Dual Boot, CFG0 - CFG1\n");
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else if (boot_mode == 1)
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printf("Dual Boot, CFG1 - CFG0\n");
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else if (boot_mode == 3)
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printf("Single Boot, CFG0\n");
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else if (boot_mode == 4)
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printf("Single Boot, CFG1\n");
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else if (boot_mode == 5)
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printf("Dual Boot, Boot from former bitstream first\n");
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else if (boot_mode == 7)
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printf("Dual Boot, Boot from latter bitstream first\n");
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else if ((boot_mode & 0x03) == 2)
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printf("Dual Boot, No Boot\n");
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else
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printf("Unknown boot sequence selection");
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} else {
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if (boot_mode == 0)
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printf("Dual Boot, CFG0 - Ext\n");
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else if ((boot_mode & 0x03) == 1)
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printf("Single Boot, Ext\n");
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else if (boot_mode == 2)
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printf("Dual Boot, Ext - CFG0\n");
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else if ((boot_mode & 0x03) == 3)
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printf("Dual Boot, Ext - Ext\n");
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else if (boot_mode == 4)
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printf("Dual Boot, CFG1 - Ext\n");
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else if (boot_mode == 6)
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printf("Dual Boot, Ext - CFG1\n");
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else
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printf("Unknown boot sequence selection");
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}
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printf("\tMSPI Enable : %s\n",
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((_feabits & FEA_MSPI_PERSIST)?"Yes":"No"));
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printf("\tI2C Disable : %s\n",
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printf("\tI2C Disable : %s\n",
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((_feabits & FEA_I2C_PERSIST)?"Yes":"No"));
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printf("\tSSPI Disable : %s\n",
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printf("\tSSPI Disable : %s\n",
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((_feabits & FEA_SSPI_PERSIST)?"Yes":"No"));
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printf("\tJTAG Disable : %s\n",
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printf("\tJTAG Disable : %s\n",
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((_feabits & FEA_JTAG_PERSIST)?"Yes":"No"));
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printf("\tDONE Enable : %s\n",
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printf("\tDONE Enable : %s\n",
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((_feabits & FEA_DONE_PERSIST)?"Yes":"No"));
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printf("\tINIT Enable : %s\n",
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printf("\tINIT Enable : %s\n",
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((_feabits & FEA_INITN_PERSIST)?"Yes":"No"));
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printf("\tPROGRAM Disable : %s\n",
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printf("\tPROGRAM Disable : %s\n",
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((_feabits & FEA_PROG_PERSIST)?"Yes":"No"));
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printf("\tCustom ID Enable : %s\n",
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printf("\tCustom ID Enable : %s\n",
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((_feabits & FEA_MY_ASSP_EN)?"Yes":"No"));
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int flash_prot = (_feabits >> 1) & 0x07;
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printf("\tFlash Protection : ");
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if (flash_prot == 0) {
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printf("None\n");
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}
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else {
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if (flash_prot & 0x04)
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printf("CFG0 & CFG1 ");
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if (flash_prot & 0x02)
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printf("Feature, Security Keys ");
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if (flash_prot & 0x01)
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printf("All UFMs");
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printf("\n");
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}
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printf("\tI2C Deglitch Filter : %s\n",
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int flash_prot = (_feabits >> 1) & 0x07;
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printf("\tFlash Protection : ");
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if (flash_prot == 0) {
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printf("None\n");
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} else {
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if (flash_prot & 0x04)
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printf("CFG0 & CFG1 ");
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if (flash_prot & 0x02)
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printf("Feature, Security Keys ");
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if (flash_prot & 0x01)
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printf("All UFMs");
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printf("\n");
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}
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printf("\tI2C Deglitch Filter : %s\n",
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((_feabits & FEA_I2C_DG_FIL_EN)?"Enabled":"Disabled"));
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}
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}
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@ -191,7 +232,7 @@ void FeaParser::displayHeader()
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*/
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void FeaParser::parseFeatureRowAndFeabits(const vector<string> &content)
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{
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printf("Parsing Feature Row & FEAbits...\n");
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printf("Parsing Feature Row & FEAbits...\n");
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string featuresRow = content[0];
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//printf("Features: [%s]\n", featuresRow.c_str());
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@ -199,7 +240,7 @@ void FeaParser::parseFeatureRowAndFeabits(const vector<string> &content)
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_featuresRow[3 - (i/32) - 1] |= ((featuresRow[i] - '0') << (32 - (i%32) - 1));
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string feabits = content[1];
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//printf("Feabits: [%s]\n", feabits.c_str());
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//printf("Feabits: [%s]\n", feabits.c_str());
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_feabits = 0;
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for (size_t i = 0; i < feabits.size(); i++) {
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_feabits |= ((feabits[i] - '0') << (feabits.size() - i - 1));
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@ -214,12 +255,12 @@ int FeaParser::parse()
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int first_pos;
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char instr;
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lines = readFeaFile();
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/* empty or end of file */
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if (lines.size() > 0) {
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parseFeatureRowAndFeabits(lines);
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_has_feabits = true;
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}
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lines = readFeaFile();
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/* empty or end of file */
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if (lines.size() > 0) {
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parseFeatureRowAndFeabits(lines);
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_has_feabits = true;
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}
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return EXIT_SUCCESS;
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}
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@ -15,48 +15,6 @@
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#include "configBitstreamParser.hpp"
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/* FEAbits element defines */
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# define FEA_I2C_DG_FIL_EN (1 << 0) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
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# define FEA_FLASH_PROT_SEC_SEL (0x7 << 1) /* Flash Protection Sector Selection */
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# define FEA_MY_ASSP_EN (1 << 4) /* MY_ASSP Enabled 0=Disabled (Default), 1=Enabled */
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# define FEA_PROG_PERSIST (1 << 5) /* PROGRAMN Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_INITN_PERSIST (1 << 6) /* INITN Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_DONE_PERSIST (1 << 7) /* DONE Persistence 0=Disabled (Default), 1=Enabled */
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# define FEA_JTAG_PERSIST (1 << 8) /* JTAG Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_SSPI_PERSIST (1 << 9) /* Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_I2C_PERSIST (1 << 10) /* I²C Port Persistence 0=Enabled (Default), 1=Disabled */
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# define FEA_MSPI_PERSIST (1 << 11) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
|
||||
# define FEA_BOOT_SEQ_SEL (0x07 << 12) /* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
|
||||
# define FEA_I2C_DG_RANGE_SEL (1 << 15) /* I2C deglitch filter range selection on primary I2C port2 0= 8 to 25 ns range (Default) 1= 16 to 50 ns range */
|
||||
# define FEA_VERSION_RB_PROT (1 << 16) /* Version Rollback Protection1 0= Disabled (Default) 1= Enabled (Checks if current version of bitstream is similar to the one that is going to be downloaded) */
|
||||
# define FEA_RESERVED_ZERO (0xffff << 17)
|
||||
|
||||
/* Feature Row element defines */
|
||||
# define FEATURE_CUSTOM_ID (0xffffffff) /* 32 bits of Custom ID code */
|
||||
|
||||
# define FEATURE_TRACE_ID (0xff << 0) /* 8 bits for the user programmable TraceID */
|
||||
# define FEATURE_I2C_SLAVE_ADDR (0xff << 8) /* 8 bits for the user programmable I2C Slave Address */
|
||||
# define FEATURE_DUAL_BOOT_ADDR (0xffff << 16) /* 16 bits for Dual boot address (Most significant 16- bit of address for secondary boot from external flash) */
|
||||
|
||||
# define FEATURE_MASTER_RETRY_CNT (0x3 << 2) /* Master Retry Count */
|
||||
# define FEATURE_MASTER_TIMER_CNT (0x0f << 4) /* Master Timer Count */
|
||||
# define FEATURE_SLAVE_IDLE_TIMER_CNT (0x0f << 8) /* Slave Idle Timer Count */
|
||||
# define FEATURE_SFDP_CONT_FAIL (1 << 14) /* SFDP Continue on Fail */
|
||||
# define FEATURE_SFDP_EN (1 << 15) /* SFDP Enable */
|
||||
# define FEATURE_BULK_ERASE_DISABLE (1 << 16) /* No Bulk Erase */
|
||||
# define FEATURE_32BIT_SPIM (1 << 17) /* 32-bit SPIM */
|
||||
# define FEATURE_MCLK_BYPASS (1 << 18) /* MCLK Bypass */
|
||||
# define FEATURE_LSBF (1 << 19) /* LSBF */
|
||||
# define FEATURE_RX_EDGE (1 << 20)
|
||||
# define FEATURE_TX_EDGE (1 << 21)
|
||||
# define FEATURE_CPOL (1 << 22)
|
||||
# define FEATURE_CPHA (1 << 23)
|
||||
# define FEATURE_HSE_CLOCK_SEL (0x3 << 24)
|
||||
# define FEATURE_EBR_ENABLE (1 << 26)
|
||||
# define FEATURE_SSPI_AUTO (1 << 28) /* SSPI Auto */
|
||||
# define FEATURE_CPU (1 << 29) /* CPU */
|
||||
# define FEATURE_CORE_CLK_SEL (0x03 << 30) /* Core Clock Sel */
|
||||
|
||||
class FeaParser: public ConfigBitstreamParser {
|
||||
public:
|
||||
FeaParser(std::string filename, bool verbose = false);
|
||||
|
|
@ -68,13 +26,13 @@ class FeaParser: public ConfigBitstreamParser {
|
|||
|
||||
private:
|
||||
std::vector<std::string>readFeaFile();
|
||||
void parseFeatureRowAndFeabits(const std::vector<std::string> &content);
|
||||
void parseFeatureRowAndFeabits(const std::vector<std::string> &content);
|
||||
|
||||
uint32_t _featuresRow[3];
|
||||
uint32_t _feabits;
|
||||
bool _has_feabits;
|
||||
|
||||
std::istringstream _ss;
|
||||
std::istringstream _ss;
|
||||
};
|
||||
|
||||
#endif // FEAPARSER_HPP_
|
||||
|
|
|
|||
228
src/lattice.cpp
228
src/lattice.cpp
|
|
@ -25,41 +25,41 @@
|
|||
|
||||
using namespace std;
|
||||
|
||||
#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
|
||||
#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
|
||||
# define ISC_ENABLE_FLASH_MODE (1 << 3)
|
||||
# define ISC_ENABLE_SRAM_MODE (0 << 3)
|
||||
#define ISC_ENABLE_TRANSPARANT 0x74 /* This command is used to put the device in transparent mode */
|
||||
#define ISC_DISABLE 0x26 /* ISC_DISABLE */
|
||||
#define READ_DEVICE_ID_CODE 0xE0 /* IDCODE_PUB */
|
||||
#define FLASH_ERASE 0x0E /* ISC_ERASE */
|
||||
#define ISC_DISABLE 0x26 /* ISC_DISABLE */
|
||||
#define READ_DEVICE_ID_CODE 0xE0 /* IDCODE_PUB */
|
||||
#define FLASH_ERASE 0x0E /* ISC_ERASE */
|
||||
/* Flash areas as defined for Lattice MachXO3L/LF */
|
||||
# define FLASH_ERASE_UFM (1<<3)
|
||||
# define FLASH_ERASE_UFM (1<<3)
|
||||
# define FLASH_ERASE_CFG (1<<2)
|
||||
# define FLASH_ERASE_FEATURE (1<<1)
|
||||
# define FLASH_ERASE_SRAM (1<<0)
|
||||
# define FLASH_ERASE_SRAM (1<<0)
|
||||
# define FLASH_ERASE_ALL 0x0F
|
||||
/* Flash areas as defined for Lattice MachXO3D, used with command: ISC_ERASE */
|
||||
# define FLASH_SEC_CFG0 (1<<8)
|
||||
# define FLASH_SEC_CFG1 (1<<9)
|
||||
# define FLASH_SEC_UFM0 (1<<10)
|
||||
# define FLASH_SEC_UFM1 (1<<11)
|
||||
# define FLASH_SEC_UFM2 (1<<12)
|
||||
# define FLASH_SEC_UFM3 (1<<13)
|
||||
// # define FLASH_SEC_CSEC (1<<14) /* not defined in later documentation */
|
||||
// # define FLASH_SEC_USEC (1<<15) /* not defined in later documentation */
|
||||
# define FLASH_SEC_PKEY (1<<16)
|
||||
# define FLASH_SEC_AKEY (1<<17)
|
||||
# define FLASH_SEC_FEA (1<<18)
|
||||
# define FLASH_SEC_ALL 0x7FF
|
||||
# define FLASH_SEC_CFG0 (1<<8)
|
||||
# define FLASH_SEC_CFG1 (1<<9)
|
||||
# define FLASH_SEC_UFM0 (1<<10)
|
||||
# define FLASH_SEC_UFM1 (1<<11)
|
||||
# define FLASH_SEC_UFM2 (1<<12)
|
||||
# define FLASH_SEC_UFM3 (1<<13)
|
||||
// # define FLASH_SEC_CSEC (1<<14) /* not defined in later documentation */
|
||||
// # define FLASH_SEC_USEC (1<<15) /* not defined in later documentation */
|
||||
# define FLASH_SEC_PKEY (1<<16)
|
||||
# define FLASH_SEC_AKEY (1<<17)
|
||||
# define FLASH_SEC_FEA (1<<18)
|
||||
# define FLASH_SEC_ALL 0x7FF
|
||||
/* This uses the same defines as above (for ISC_ERASE)
|
||||
* The Lattice Standard Doc for MachXO3D has incorrect list of operands for this
|
||||
* command.
|
||||
* This is document is more correct:
|
||||
* fpga-tn-02119-1-1-using-hardened-control-functions-machxo3d-reference.pdf
|
||||
*/
|
||||
#define RESET_CFG_ADDR 0x46 /* LSC_INIT_ADDRESS */
|
||||
#define RESET_CFG_ADDR 0x46 /* LSC_INIT_ADDRESS */
|
||||
/* Set the Page Address pointer to the Flash page specified */
|
||||
#define LSC_WRITE_ADDRESS 0xB4
|
||||
#define LSC_WRITE_ADDRESS 0xB4
|
||||
# define FLASH_SET_ADDR_CFG0 0x00
|
||||
# define FLASH_SET_ADDR_UFM0 0x01
|
||||
# define FLASH_SET_ADDR_FEA 0x03
|
||||
|
|
@ -74,63 +74,63 @@ using namespace std;
|
|||
/* Set the Page Address Pointer to the beginning of the UFM sectors.
|
||||
* It appears that this function is required when setting address to UFM sectors
|
||||
* The LSC_INIT_ADDRESS doesn't work when the sector is set to UFMx ... */
|
||||
#define LSC_INIT_ADDR_UFM 0x47
|
||||
#define LSC_INIT_ADDR_UFM 0x47
|
||||
# define FLASH_UFM_ADDR_UFM0 (1<<10)
|
||||
# define FLASH_UFM_ADDR_UFM1 (1<<11)
|
||||
# define FLASH_UFM_ADDR_UFM2 (1<<12)
|
||||
# define FLASH_UFM_ADDR_UFM3 (1<<13)
|
||||
#define PROG_CFG_FLASH 0x70 /* LSC_PROG_INCR_NV */
|
||||
#define READ_BUSY_FLAG 0xF0 /* LSC_CHECK_BUSY */
|
||||
#define PROG_CFG_FLASH 0x70 /* LSC_PROG_INCR_NV */
|
||||
#define READ_BUSY_FLAG 0xF0 /* LSC_CHECK_BUSY */
|
||||
/* The busy flag defines bit 7 as busy, but busy flags returns 1 for busy (bit 0). */
|
||||
#define REG_CFG_FLASH 0x73 /* LSC_READ_INCR_NV */
|
||||
#define PROG_FEATURE_ROW 0xE4 /* LSC_PROG_FEATURE */
|
||||
#define READ_FEATURE_ROW 0xE7 /* LSC_READ_FEATURE */
|
||||
#define REG_CFG_FLASH 0x73 /* LSC_READ_INCR_NV */
|
||||
#define PROG_FEATURE_ROW 0xE4 /* LSC_PROG_FEATURE */
|
||||
#define READ_FEATURE_ROW 0xE7 /* LSC_READ_FEATURE */
|
||||
/* See feaParser.hpp for FEATURE definitions */
|
||||
#define PROG_FEABITS 0xF8 /* LSC_PROG_FEABITS */
|
||||
#define READ_FEABITS 0xFB /* LSC_READ_FEABITS */
|
||||
#define PROG_FEABITS 0xF8 /* LSC_PROG_FEABITS */
|
||||
#define READ_FEABITS 0xFB /* LSC_READ_FEABITS */
|
||||
/* See feaParser.hpp for FEAbit definitions */
|
||||
#define PROG_DONE 0x5E /* ISC_PROGRAM_DONE - This command is used to program the done bit */
|
||||
#define REFRESH 0x79 /* LSC_REFRESH */
|
||||
#define READ_STATUS_REGISTER 0x3C /* LSC_READ_STATUS */
|
||||
# define REG_STATUS_DONE (1 << 8) /* Flash or SRAM Done Flag (ISC_EN=0 -> 1 Successful Flash to SRAM transfer, ISC_EN=1 -> 1 Programmed) */
|
||||
# define REG_STATUS_ISC_EN (1 << 9) /* Enable Configuration Interface (1=Enable, 0=Disable) */
|
||||
# define REG_STATUS_BUSY (1 << 12) /* Busy Flag (1 = Busy) */
|
||||
# define REG_STATUS_FAIL (1 << 13) /* Fail Flag (1 = Operation failed) */
|
||||
# define REG_STATUS_PP_CFG (1 << 15) /* Password Protection All Enabled for CFG0 and CFG1 flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS_PP_FSK (1 << 16) /* Password Protection Enabled for Feature and Security Key flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS_PP_UFM (1 << 17) /* Password Protection enabled for all UFM flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
#define PROG_DONE 0x5E /* ISC_PROGRAM_DONE - This command is used to program the done bit */
|
||||
#define REFRESH 0x79 /* LSC_REFRESH */
|
||||
#define READ_STATUS_REGISTER 0x3C /* LSC_READ_STATUS */
|
||||
# define REG_STATUS_DONE (1 << 8) /* Flash or SRAM Done Flag (ISC_EN=0 -> 1 Successful Flash to SRAM transfer, ISC_EN=1 -> 1 Programmed) */
|
||||
# define REG_STATUS_ISC_EN (1 << 9) /* Enable Configuration Interface (1=Enable, 0=Disable) */
|
||||
# define REG_STATUS_BUSY (1 << 12) /* Busy Flag (1 = Busy) */
|
||||
# define REG_STATUS_FAIL (1 << 13) /* Fail Flag (1 = Operation failed) */
|
||||
# define REG_STATUS_PP_CFG (1 << 15) /* Password Protection All Enabled for CFG0 and CFG1 flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS_PP_FSK (1 << 16) /* Password Protection Enabled for Feature and Security Key flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS_PP_UFM (1 << 17) /* Password Protection enabled for all UFM flash sectors 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */
|
||||
# define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */
|
||||
# define REG_STATUS_CNF_CHK_MASK (0x0f << 22)/* Configuration Status Check */
|
||||
# define REG_STATUS_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */
|
||||
# define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/
|
||||
# define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */
|
||||
#define READ_STATUS_REGISTER_1 0x3D /* LSC_READ_STATUS_1 */
|
||||
#define READ_STATUS_REGISTER_1 0x3D /* LSC_READ_STATUS_1 */
|
||||
# define REG_STATUS1_FLASH_SEL (0x0f << 0) /* Flash sector selection 1=CFG0, 2=CFG1, 4=FEATURE, 5=Pub Key, 6=AES Key, 8=UFM0, 10=UFM1, 11=UFM2, 12=UFM3 */
|
||||
# define REG_STATUS1_ERASE_DISABLE (1 << 4) /* Erase operation is prohibited (1 = Erase disable) */
|
||||
# define REG_STATUS1_PROG_DISABLE (1 << 5) /* Program operation is prohibited (1 = Programing disable) */
|
||||
# define REG_STATUS1_READ_DISABLE (1 << 6) /* Read operation is prohibited (1 = Read disable) */
|
||||
# define REG_STATUS1_HS_LOCK_SEL (1 << 7) /* Hard/Soft Lock Selection (1 = Hard Lock, 0 = Soft Lock) */
|
||||
# define REG_STATUS1_AUTH_MODE (0x03 << 8) /* Authentication mode: 0x: No Authentication, 10: HMAC Authentication, 11: ECDSA Signature Verification */
|
||||
# define REG_STATUS1_AUTH_DONE_CFG0 (1 << 10) /* Authentication done for CFG0 (1 = Authentication successful) */
|
||||
# define REG_STATUS1_AUTH_DONE_CFG1 (1 << 11) /* Authentication done for CFG1 (1 = Authentication successful) */
|
||||
# define REG_STATUS1_FLASH_DONE_CFG0 (1 << 12) /* Flash done bit is programmed of CFG0 (1= Programmed, 0=Unprogrammed) */
|
||||
# define REG_STATUS1_FLASH_DONE_CFG1 (1 << 13) /* Flash done bit is programmed of CFG1 (1= Programmed, 0=Unprogrammed) */
|
||||
# define REG_STATUS1_SEC_PLUS_EN_CFG0 (1 << 14) /* Security Plus enabled for CFG0 (1 = Enabled, 0 = Disabled) */
|
||||
# define REG_STATUS1_SEC_PLUS_EN_CFG1 (1 << 15) /* Security Plus enabled for CFG1 (1 = Enabled, 0 = Disabled) */
|
||||
# define REG_STATUS1_BITSTR_VERSION (1 << 16) /* Bitstream version: 1 = Bitstream in CFG0 is latter (newer) than CFG1, 0 = Bitstream in CFG1 is latter (newer) than CFG0 */
|
||||
# define REG_STATUS1_BOOT_SEQ_SEL (0x03 << 17)/* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
|
||||
# define REG_STATUS1_AUTH_DONE_CFG0 (1 << 10) /* Authentication done for CFG0 (1 = Authentication successful) */
|
||||
# define REG_STATUS1_AUTH_DONE_CFG1 (1 << 11) /* Authentication done for CFG1 (1 = Authentication successful) */
|
||||
# define REG_STATUS1_FLASH_DONE_CFG0 (1 << 12) /* Flash done bit is programmed of CFG0 (1= Programmed, 0=Unprogrammed) */
|
||||
# define REG_STATUS1_FLASH_DONE_CFG1 (1 << 13) /* Flash done bit is programmed of CFG1 (1= Programmed, 0=Unprogrammed) */
|
||||
# define REG_STATUS1_SEC_PLUS_EN_CFG0 (1 << 14) /* Security Plus enabled for CFG0 (1 = Enabled, 0 = Disabled) */
|
||||
# define REG_STATUS1_SEC_PLUS_EN_CFG1 (1 << 15) /* Security Plus enabled for CFG1 (1 = Enabled, 0 = Disabled) */
|
||||
# define REG_STATUS1_BITSTR_VERSION (1 << 16) /* Bitstream version: 1 = Bitstream in CFG0 is latter (newer) than CFG1, 0 = Bitstream in CFG1 is latter (newer) than CFG0 */
|
||||
# define REG_STATUS1_BOOT_SEQ_SEL (0x03 << 17) /* Boot Sequence selection (used along with Master SPI Port Persistence bit) */
|
||||
# define REG_STATUS1_MSPI_PERS (1 << 20) /* Master SPI Port Persistence 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS1_I2C_DG_FILTER (1 << 21) /* I2C deglitch filter enable for Primary I2C Port 0=Disabled (Default), 1=Enabled */
|
||||
# define REG_STATUS1_I2C_DG_RANGE (1 << 22) /* I2C deglitch filter range selection on primary I2C port 0= 8 to 25 ns range (Default), 1= 16 to 50 ns range */
|
||||
#define PROG_ECDSA_PUBKEY0 0x59 /* This command is used to program the first 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY0 0x5A /* This command is used to read the first 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY1 0x5B /* This command is used to program the second 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY1 0x5C /* This command is used to read the second 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY2 0x61 /* This command is used to program the third 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY2 0x62 /* This command is used to read the third 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY3 0x63 /* This command is used to program the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY3 0x64 /* This command is used to read the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define ISC_NOOP 0xff /* This command is no operation command (NOOP) or null operation. */
|
||||
#define PROG_ECDSA_PUBKEY0 0x59 /* This command is used to program the first 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY0 0x5A /* This command is used to read the first 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY1 0x5B /* This command is used to program the second 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY1 0x5C /* This command is used to read the second 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY2 0x61 /* This command is used to program the third 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY2 0x62 /* This command is used to read the third 128 bits of the ECDSA Public Key. */
|
||||
#define PROG_ECDSA_PUBKEY3 0x63 /* This command is used to program the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define READ_ECDSA_PUBKEY3 0x64 /* This command is used to read the fourth 128 bits of the ECDSA Public Key. */
|
||||
#define ISC_NOOP 0xff /* This command is no operation command (NOOP) or null operation. */
|
||||
|
||||
Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
|
||||
Device::prog_type_t prg_type, std::string flash_sector, bool verify, int8_t verbose):
|
||||
|
|
@ -158,9 +158,35 @@ Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
|
|||
_fpga_family = MACHXO2_FAMILY;
|
||||
else if (family == "MachXO3LF")
|
||||
_fpga_family = MACHXO3_FAMILY;
|
||||
else if (family == "MachXO3D")
|
||||
_fpga_family = MACHXO3D_FAMILY;
|
||||
else if (family == "ECP5")
|
||||
else if (family == "MachXO3D") {
|
||||
_fpga_family = MACHXO3D_FAMILY;
|
||||
|
||||
if (flash_sector == "CFG0") {
|
||||
_flash_sector = LATTICE_FLASH_CFG0;
|
||||
printInfo("Flash Sector: CFG0", true);
|
||||
} else if (flash_sector == "CFG1") {
|
||||
_flash_sector = LATTICE_FLASH_CFG1;
|
||||
printInfo("Flash Sector: CFG1", true);
|
||||
} else if (flash_sector == "UFM0") {
|
||||
_flash_sector = LATTICE_FLASH_UFM0;
|
||||
printInfo("Flash Sector: UFM0", true);
|
||||
} else if (flash_sector == "UFM1") {
|
||||
_flash_sector = LATTICE_FLASH_UFM1;
|
||||
printInfo("Flash Sector: UFM1", true);
|
||||
} else if (flash_sector == "UFM2") {
|
||||
_flash_sector = LATTICE_FLASH_UFM2;
|
||||
printInfo("Flash Sector: UFM2", true);
|
||||
} else if (flash_sector == "UFM3") {
|
||||
_flash_sector = LATTICE_FLASH_UFM3;
|
||||
printInfo("Flash Sector: UFM3", true);
|
||||
} else if (flash_sector == "FEA") {
|
||||
_flash_sector = LATTICE_FLASH_FEA;
|
||||
printInfo("Flash Sector: FEA", true);
|
||||
} else {
|
||||
printError("Unknown flash sector");
|
||||
throw std::exception();
|
||||
}
|
||||
} else if (family == "ECP5")
|
||||
_fpga_family = ECP5_FAMILY;
|
||||
else if (family == "CrosslinkNX")
|
||||
_fpga_family = NEXUS_FAMILY;
|
||||
|
|
@ -170,39 +196,6 @@ Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
|
|||
printError("Unknown device family");
|
||||
throw std::exception();
|
||||
}
|
||||
|
||||
if (flash_sector == "CFG0") {
|
||||
_flash_sector = LATTICE_FLASH_CFG0;
|
||||
printInfo("Flash Sector: CFG0", true);
|
||||
}
|
||||
else if (flash_sector == "CFG1") {
|
||||
_flash_sector = LATTICE_FLASH_CFG1;
|
||||
printInfo("Flash Sector: CFG1", true);
|
||||
}
|
||||
else if (flash_sector == "UFM0") {
|
||||
_flash_sector = LATTICE_FLASH_UFM0;
|
||||
printInfo("Flash Sector: UFM0", true);
|
||||
}
|
||||
else if (flash_sector == "UFM1") {
|
||||
_flash_sector = LATTICE_FLASH_UFM1;
|
||||
printInfo("Flash Sector: UFM1", true);
|
||||
}
|
||||
else if (flash_sector == "UFM2") {
|
||||
_flash_sector = LATTICE_FLASH_UFM2;
|
||||
printInfo("Flash Sector: UFM2", true);
|
||||
}
|
||||
else if (flash_sector == "UFM3") {
|
||||
_flash_sector = LATTICE_FLASH_UFM3;
|
||||
printInfo("Flash Sector: UFM3", true);
|
||||
}
|
||||
else if (flash_sector == "FEA") {
|
||||
_flash_sector = LATTICE_FLASH_FEA;
|
||||
printInfo("Flash Sector: FEA", true);
|
||||
}
|
||||
else {
|
||||
printError("Unknown flash sector");
|
||||
throw std::exception();
|
||||
}
|
||||
}
|
||||
|
||||
void displayFeabits(uint16_t _featbits)
|
||||
|
|
@ -619,9 +612,6 @@ bool Lattice::program_flash(unsigned int offset)
|
|||
else if (_file_extension == "fea") {
|
||||
retval = program_fea_MachXO3D();
|
||||
}
|
||||
else if (_file_extension == "pub") {
|
||||
retval = program_pubkey_MachXO3D();
|
||||
}
|
||||
else
|
||||
retval = program_extFlash(offset);
|
||||
|
||||
|
|
@ -1541,52 +1531,6 @@ bool Lattice::program_fea_MachXO3D()
|
|||
return true;
|
||||
}
|
||||
|
||||
bool Lattice::program_pubkey_MachXO3D()
|
||||
{
|
||||
bool err;
|
||||
bool same = true;
|
||||
int len;
|
||||
|
||||
RawParser _pk(_filename, false);
|
||||
printInfo("Open file: ", false);
|
||||
printSuccess("DONE");
|
||||
|
||||
err = _pk.parse();
|
||||
printInfo("Parse file: ", false);
|
||||
if (err == EXIT_FAILURE) {
|
||||
printError("FAIL");
|
||||
return false;
|
||||
} else {
|
||||
printSuccess("DONE");
|
||||
}
|
||||
|
||||
uint8_t* data = _pk.getData();
|
||||
len = _pk.getLength()/8;
|
||||
|
||||
printf("Header: [");
|
||||
if (data[0] == 0x0f) {
|
||||
for (int i = 2; i < len; i++) {
|
||||
if (data[i] == 0xf0)
|
||||
break;
|
||||
printf("%c", data[i]);
|
||||
}
|
||||
}
|
||||
printf("]\n");
|
||||
|
||||
printf("Data: [");
|
||||
for (int i = 0; i < len -3; i++) {
|
||||
printf("0x%02x ", data[i]);
|
||||
}
|
||||
printf("\b]\n");
|
||||
|
||||
printf("Trailing bytes: [");
|
||||
for (int i = len -3; i < len; i++) {
|
||||
printf("0x%02x ", data[i]);
|
||||
}
|
||||
printf("\b]\n");
|
||||
|
||||
}
|
||||
|
||||
bool Lattice::program_intFlash_MachXO3D()
|
||||
{
|
||||
bool err, ufm_flag;
|
||||
|
|
|
|||
|
|
@ -98,7 +98,6 @@ class Lattice: public Device, SPIInterface {
|
|||
lattice_flash_sector_t _flash_sector;
|
||||
bool program_intFlash_MachXO3D();
|
||||
bool program_fea_MachXO3D();
|
||||
bool program_pubkey_MachXO3D();
|
||||
bool programFeatureRow_MachXO3D(uint8_t* feature_row);
|
||||
bool programFeabits_MachXO3D(uint32_t feabits);
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue