xilinx: adapted code to support existing spiOverJtag bitstreams (v1) and new bitstreams (v2)
This commit is contained in:
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
parent
971a8db4e9
commit
03045dc407
142
src/xilinx.cpp
142
src/xilinx.cpp
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@ -37,6 +37,7 @@
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/* Used for xc3s */
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#define USER1 0x02
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#define USER4 0x23
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#define CFG_IN 0x05
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#define USERCODE 0x08
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#define IDCODE 0x09
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@ -278,7 +279,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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SPIInterface(filename, verbose, 256, verify, skip_load_bridge,
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skip_reset),
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_device_package(device_package), _spiOverJtagPath(spiOverJtagPath),
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_irlen(6), _secondary_filename(secondary_filename)
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_irlen(6), _secondary_filename(secondary_filename), _soj_is_v2(false),
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_jtag_chain_len(1)
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{
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if (prg_type == Device::RD_FLASH) {
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_mode = Device::READ_MODE;
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@ -673,11 +675,24 @@ bool Xilinx::post_flash_access()
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bool Xilinx::prepare_flash_access()
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{
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bool ret = false;
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if (_skip_load_bridge) {
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printInfo("Skip loading bridge for spiOverjtag");
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return true;
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ret = true;
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} else {
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ret = load_bridge();
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}
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return load_bridge();
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/* Get number of FPGAs in the Jtag Chain */
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_jtag_chain_len = _jtag->get_chain_len();
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/* check SpiOverJtag version */
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if (ret) {
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if (get_spiOverJtag_version() == 2.0f)
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_soj_is_v2 = true;
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printf("SOJ version: %f\n", _soj_is_v2 ? 2.0f : 1.0f);
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}
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return ret;
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}
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bool Xilinx::load_bridge()
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@ -714,9 +729,32 @@ bool Xilinx::load_bridge()
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printError(e.what());
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throw std::runtime_error(e.what());
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}
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return true;
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}
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float Xilinx::get_spiOverJtag_version()
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{
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uint8_t jtx[6] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00};
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uint8_t jrx[7];
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uint8_t rx[6];
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_jtag->shiftIR(USER4, _irlen, Jtag::UPDATE_IR);
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printf("jtag_chain_len: %d\n", _jtag_chain_len);
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if (_jtag_chain_len > 1)
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_jtag->shiftDR(jtx, NULL, _jtag_chain_len - 1, Jtag::SHIFT_DR);
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_jtag->shiftDR(jtx, jrx, 6 * 8);
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_jtag->flush();
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memcpy(rx, &jrx[1], 5);
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rx[5] = '\0';
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float version = atof((const char *)rx);
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if (version == 0.0f) // not supported => 1.0
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return 1.0f;
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return version;
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}
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void Xilinx::program_spi(ConfigBitstreamParser * bit, unsigned int offset,
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bool unprotect_flash)
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{
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@ -2023,6 +2061,10 @@ bool Xilinx::xc2c_flow_program(JedParser *jed)
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int Xilinx::spi_put(uint8_t cmd,
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const uint8_t *tx, uint8_t *rx, uint32_t len)
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{
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/* SpiOverJtag v2 */
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if (_soj_is_v2)
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return spi_put_v2(cmd, tx, rx, len);
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int xfer_len = len + 1 + ((rx == NULL) ? 0 : 1);
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uint8_t jtx[xfer_len];
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jtx[0] = McsParser::reverseByte(cmd);
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@ -2075,28 +2117,37 @@ int Xilinx::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint32_t timeout, bool verbose)
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{
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uint8_t rx[2];
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uint8_t dummy[2];
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memset(dummy, 0xff, sizeof(dummy));
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uint8_t tx[2];
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uint8_t tmp;
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uint8_t tx = McsParser::reverseByte(cmd);
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uint32_t count = 0;
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const uint8_t shift = _jtag_chain_len;
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uint8_t idx = 0;
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if (_soj_is_v2)
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tx[idx++] = (0x2 << 1) | 1;
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tx[idx++] = McsParser::reverseByte(cmd);
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_jtag->shiftIR(get_ircode(_ircode_map, _user_instruction), NULL, _irlen, Jtag::UPDATE_IR);
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_jtag->shiftDR(&tx, NULL, 8, Jtag::SHIFT_DR);
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_jtag->shiftDR(tx, NULL, 8 * idx, Jtag::SHIFT_DR);
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do {
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_jtag->shiftDR(dummy, rx, 8*2, Jtag::SHIFT_DR);
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tmp = (McsParser::reverseByte(rx[0]>>1)) | (0x01 & rx[1]);
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_jtag->shiftDR(tx, rx, 8*2, Jtag::SHIFT_DR);
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tmp = McsParser::reverseByte(rx[0 ]>> shift);
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if (shift == 1)
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tmp |= (0x01 & rx[1]);
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else
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tmp |= McsParser::reverseByte(rx[1]) >> (8 - shift);
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count++;
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if (count == timeout){
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printf("timeout: %x %x %x\n", tmp, rx[0], rx[1]);
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break;
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}
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if (verbose) {
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printf("%x %x %x %u\n", tmp, mask, cond, count);
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printf("%x %x %x %u %02x %02x\n", tmp, mask, cond, count, rx[0], rx[1]);
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}
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} while ((tmp & mask) != cond);
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_jtag->shiftDR(dummy, rx, 8*2, Jtag::EXIT1_DR);
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_jtag->shiftDR(tx, rx, 8 * 2, Jtag::EXIT1_DR);
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_jtag->go_test_logic_reset();
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if (count == timeout) {
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@ -2108,6 +2159,75 @@ int Xilinx::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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}
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}
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int Xilinx::spi_put_v2(uint8_t cmd, const uint8_t *tx, uint8_t *rx,
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uint32_t len)
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{
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const uint32_t real_len = len + 1; // rx/tx length + cmd
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uint32_t kPktLen = real_len + 2; // One header and +1 due to the needs of an additional bit/byte
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uint8_t mode = 0x01;
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if (real_len > 32) {
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kPktLen++; // Additional header
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mode = 0x00;
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}
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const uint32_t xfer_bit_len = (kPktLen - 1) * 8 + (rx ? 8 : 1);
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uint8_t jrx[kPktLen];
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uint8_t pkt[kPktLen];
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uint32_t idx = 0;
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pkt[idx++] = ((0x1f & real_len) << 3) | ((0x03 & mode) << 1) | 1;
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if (mode == 0x00)
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pkt[idx++] = 0xff & (real_len >> 5);
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pkt[idx++] = McsParser::reverseByte(cmd);
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if (tx) {
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for (uint32_t i=0; i < len; i++)
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pkt[idx++] = McsParser::reverseByte(tx[i]);
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} else {
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memset(&pkt[idx], 0, len);
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idx += len;
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}
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/* addr BSCAN user1 */
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_jtag->shiftIR(get_ircode(_ircode_map, _user_instruction), NULL, _irlen);
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_jtag->shiftDR(pkt, (rx == NULL) ? NULL : jrx, xfer_bit_len);
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_jtag->go_test_logic_reset();
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_jtag->flush();
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if (_verbose) {
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for (uint32_t i = 0; i < kPktLen; i++)
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printf("%02x ", pkt[i]);
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printf("\n");
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}
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if (rx != NULL) {
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if (_verbose) {
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for (uint32_t i = 0; i < kPktLen; i++)
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printf("%02x ", jrx[i]);
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printf("\n");
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for (uint32_t i = 0; i < kPktLen; i++)
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printf("%02x ", McsParser::reverseByte(jrx[i]));
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printf("\n");
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}
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idx = (mode == 0 ? 3 : 2);
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const uint8_t shift = _jtag_chain_len;
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for (uint32_t i = 0; i < len; i++) {
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rx[i] = McsParser::reverseByte(jrx[i + idx] >> shift);
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if (shift == 1)
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rx[i] |= (jrx[i + idx + 1] & 0x01);
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else
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rx[i] |= McsParser::reverseByte(jrx[i + idx + 1]) >> (8 - shift);
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if (_verbose)
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printf("%02x ", rx[i]);
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}
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if (_verbose)
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printf("\n");
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}
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return 0;
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}
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void Xilinx::select_flash_chip(xilinx_flash_chip_t flash_chip) {
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switch (flash_chip) {
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case SECONDARY_FLASH:
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@ -168,6 +168,10 @@ class Xilinx: public Device, SPIInterface {
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int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint32_t timeout, bool verbose = false) override;
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/* SpiOverJtag v2 specifics methods */
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int spi_put_v2(uint8_t cmd, const uint8_t *tx, uint8_t *rx,
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uint32_t len);
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protected:
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/*!
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* \brief prepare SPI flash access (need to have bridge in RAM)
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@ -215,6 +219,12 @@ class Xilinx: public Device, SPIInterface {
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*/
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bool load_bridge();
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/*!
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* \brief read SpiOverJtag version to select between v1 and v2
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* \return 2.0 for v2 or 1.0 for v1
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*/
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float get_spiOverJtag_version();
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enum xilinx_flash_chip_t {
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PRIMARY_FLASH = 0x1,
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SECONDARY_FLASH = 0x2
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@ -249,6 +259,8 @@ class Xilinx: public Device, SPIInterface {
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std::string _secondary_file_extension; /* file type for the secondary flash file */
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int _flash_chips; /* bitfield to select the target in boards with two flash chips */
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std::string _user_instruction; /* which USER bscan instruction to interface with SPI */
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bool _soj_is_v2; /* SpiOverJtag version (1.0 or 2.0) */
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uint32_t _jtag_chain_len; /* Jtag Chain Length */
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};
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#endif // SRC_XILINX_HPP_
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