<aclass="extlink-ghsrc reference external"href="https://github.com/trabucayre/openFPGALoader/blob/master/spiOverJtag">spiOverJtag</a> to check if your model is supported.</p></li>
<li><p>Board provides the device/package model, but if the targeted board is not officially supported but the FPGA yes,
you can use <codeclass="docutils literal notranslate"><spanclass="pre">--fpga-part</span></code> to provide the model.</p></li>
<li><p>With spartan3, the flash is an independent JTAG device.
User has to use <codeclass="docutils literal notranslate"><spanclass="pre">--index-chain</span></code> to access FPGA (RAM only) or flash (write/read only).</p></li>
</ol>
</div>
<divclass="admonition warning">
<pclass="admonition-title">Warning</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">*.bin</span></code> may be loaded in memory or in flash, but this extension is a classic extension for CPU firmware and, by
default, <em>openFPGALoader</em> loads file in memory.
Double check <codeclass="docutils literal notranslate"><spanclass="pre">-m</span></code> / <codeclass="docutils literal notranslate"><spanclass="pre">-f</span></code> when you want to use a firmware for a softcore (or anything, other than a bitstream) to
write somewhere in the FLASH device).</p>
</div>
<p><codeclass="docutils literal notranslate"><spanclass="pre">.bit</span></code> file is the default format generated by <em>vivado</em>, so nothing special task must be done to generate this
bitstream.</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">.bin</span></code> is not, by default, produced.
To have access to this file you need to configure the tool:</p>
<li><p>TCL: append your <em>TCL</em> file with <codeclass="docutils literal notranslate"><spanclass="pre">set_property</span><spanclass="pre">STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE</span><spanclass="pre">true</span><spanclass="pre">[get_runs</span><spanclass="pre">impl_1]</span></code>.</p></li>
</ul>
<divclass="admonition warning">
<pclass="admonition-title">Warning</p>
<p>For alchitry board the bitstream must be configured with a buswidth of 1 or 2.
Quad mode can’t be used with alchitry’s FLASH.</p>
</div>
<divclass="admonition warning">
<pclass="admonition-title">Warning</p>
<p>For boards based on a Zynq (7000 or MPSoC), boot mode must be configured for JTAG (for Zedboard JP7->JP11 must be
to GND).</p>
</div>
<sectionid="loading-a-bitstream">
<h2>Loading a bitstream<aclass="headerlink"href="#loading-a-bitstream"title="Link to this heading">¶</a></h2>
<p><codeclass="docutils literal notranslate"><spanclass="pre">.bit</span></code> and <codeclass="docutils literal notranslate"><spanclass="pre">.bin</span></code> are allowed to be loaded in memory.</p>
<h3>SPI flash<aclass="headerlink"href="#spi-flash"title="Link to this heading">¶</a></h3>
<divclass="admonition note">
<pclass="admonition-title">Note</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">.bit</span></code>, <codeclass="docutils literal notranslate"><spanclass="pre">.bin</span></code>, and <codeclass="docutils literal notranslate"><spanclass="pre">.mcs</span></code> are supported for FLASH.</p>
</div>
<p><codeclass="docutils literal notranslate"><spanclass="pre">.mcs</span></code> must be generated through Vivado with a tcl script like:</p>
<divclass="admonition warning">
<pclass="admonition-title">Warning</p>
<p>For boards based on Zynq device (7000 and MPSoC) SPI flash is not accessible through PL.</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">-interface</span><spanclass="pre">spix4</span></code> and <codeclass="docutils literal notranslate"><spanclass="pre">-size</span><spanclass="pre">16</span></code> depends on SPI flash capability and size.</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">-f</span></code> is required to write bitstream (without them <codeclass="docutils literal notranslate"><spanclass="pre">.bit</span></code> and <codeclass="docutils literal notranslate"><spanclass="pre">.bin</span></code> are loaded in memory).</p>
</div>
<divclass="admonition note">
<pclass="admonition-title">Note</p>
<p><codeclass="docutils literal notranslate"><spanclass="pre">--fpga-part</span></code> is only required if this information is not provided at <codeclass="docutils literal notranslate"><spanclass="pre">board.hpp</span></code> level or if the board is not
officially supported.
device/package format is something like xc7a35tcsg324 (arty model).
See <aclass="extlink-ghsrc reference external"href="https://github.com/trabucayre/openFPGALoader/blob/master/src/board.hpp">src/board.hpp</a>, or <aclass="extlink-ghsrc reference external"href="https://github.com/trabucayre/openFPGALoader/blob/master/spiOverJtag">spiOverJtag</a> directory for examples.</p>
<p>Some boards with UltraScale FPGAs, like the VCU118 and KCU16, support the SPIx8 (Dual Quad SPI) configuration.
In this case, the <codeclass="docutils literal notranslate"><spanclass="pre">spix8</span></code> option <codeclass="docutils literal notranslate"><spanclass="pre">write_cfgmem</span></code> on the above example can be used to generate two <codeclass="docutils literal notranslate"><spanclass="pre">.mcs</span></code> files,
to fit bigger designs or for faster programming. Only <codeclass="docutils literal notranslate"><spanclass="pre">.mcs</span></code> files can be used to program the FPGA in this case.</p>
<p>In this case, to load the two <codeclass="docutils literal notranslate"><spanclass="pre">.mcs</span></code> files:</p>
<p>On these boards, each SPI flash can be programmed independently with the <codeclass="docutils literal notranslate"><spanclass="pre">--target-flash</span></code> option.
The default target is the <codeclass="docutils literal notranslate"><spanclass="pre">primary</span></code> flash.</p>
<p>For example, to program only the secondary flash with arbitrary data not related to FPGA configuration:</p>
