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< section id = "fpgas" >
< span id = "compatibility-fpgas" > < / span > < h1 > FPGAs< a class = "headerlink" href = "#fpgas" title = "Link to this heading" > ¶< / a > < / h1 >
< table class = "docutils align-default" >
< thead >
< tr class = "row-odd" > < th class = "head" > < p > Vendor< / p > < / th >
< th class = "head" > < p > Description< / p > < / th >
< th class = "head" > < p > Model< / p > < / th >
< th class = "head" > < p > Memory< / p > < / th >
< th class = "head" > < p > Flash< / p > < / th >
< / tr >
< / thead >
< tbody >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/anlogic.html#anlogic" > < span class = "std std-ref" > Anlogic< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.anlogic.com/en/product/fpga/saleagle/eg4" > EG4< / a > < / p > < / td >
< td > < p > EG4D20, EG4S20< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > AS< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/anlogic.html#anlogic" > < span class = "std std-ref" > Anlogic< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.anlogic.com/en/product/fpga/salelf/salelf2" > SALELF 2< / a > < / p > < / td >
< td > < p > EF2M45< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/colognechip.html#colognechip" > < span class = "std std-ref" > Cologne Chip< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://colognechip.com/programmable-logic/gatemate/" > GateMate Series< / a > < / p > < / td >
< td > < p > CCGM1A1, CCGM1A2, CCGM1A4, CCGM1A9, CCGM1A16, CCGM1A25< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/efinix.html#efinix" > < span class = "std std-ref" > Efinix< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.efinixinc.com/products-trion.html" > Trion< / a > < / p > < / td >
< td > < p > T8, T13, T120< / p > < / td >
< td > < p > NA< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/efinix.html#efinix" > < span class = "std std-ref" > Efinix< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.efinixinc.com/products-titanium.html" > Titanium< / a > < / p > < / td >
< td > < p > Ti60, Ti180< / p > < / td >
< td > < p > NA< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/gowin.html#gowin" > < span class = "std std-ref" > Gowin< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.gowinsemi.com/en/product/detail/46/" > LittleBee (GW1N)< / a > < / p > < / td >
< td > < p > GW1N-1, GW1N-4, GW1NR-9, GW1NR-9C, GW1NS-2C, GW1NSR-4C, GW1NZ-1< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > IF< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/gowin.html#gowin" > < span class = "std std-ref" > Gowin< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.gowinsemi.com/en/product/detail/38/" > Arora (GW2A)< / a > < / p > < / td >
< td > < p > GW2A-18C, GW2A-55< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > EF< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/gowin.html#gowin" > < span class = "std std-ref" > Gowin< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.gowinsemi.com/en/product/detail/60/" > Arora V (GW5A)< / a > < / p > < / td >
< td > < p > GW5A-25, GW5AST-138, GW5AT-15, GW5AT-60, GW5AT-138< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > EF< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/max-ii-support.html" > Max II(CPLD)< / a > < / p > < / td >
< td > < p > EPM240T100C5N< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/cyclone-ii-support.html" > Cyclone II< / a > < / p > < / td >
< td > < p > EP2C5T144C8N< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html" > Cyclone III< / a > < / p > < / td >
< td > < p > EP3C16< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html" > Cyclone IV CE< / a > < / p > < / td >
< td > < p > EP4CE22, EP4CE115< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/products/details/fpga/cyclone/iv/gx/products.html" > Cyclone IV GX< / a > < / p > < / td >
< td > < p > EP4CGX150< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html" > Cyclone V E< / a > < / p > < / td >
< td > < p > 5CEA2, 5CEA5, 5CEBA4, 5CEBA9< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html" > Cyclone V SE SoC< / a > < / p > < / td >
< td > < p > 5CSEBA6, 5CSEMA4, 5CSEMA5< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > NT< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html" > Stratix V GS< / a > < / p > < / td >
< td > < p > 5SGSD5< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html" > Cyclone 10 LP< / a > < / p > < / td >
< td > < p > 10CL025< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/intel.html#intel" > < span class = "std std-ref" > Intel< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.intel.fr/content/www/fr/fr/products/details/fpga/max/10.html" > Max 10< / a > < / p > < / td >
< td > < p > 10M02, 10M08, 10M16, 10M25< / p > < / td >
< td > < p > SVF< / p > < / td >
< td > < p > POF< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/Products/FPGAandCPLD/Certus-NX" > Certus-NX< / a > < / p > < / td >
< td > < p > LFD2NX-40< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/Products/FPGAandCPLD/Certus-NX" > CertusPro-NX< / a > < / p > < / td >
< td > < p > LFCPNX-100< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX" > CrossLink-NX< / a > < / p > < / td >
< td > < p > LIFCL-40< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3" > ECP3< / a > < / p > < / td >
< td > < p > LFE3-70E< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "http://www.latticesemi.com/Products/FPGAandCPLD/ECP5" > ECP5< / a > < / p > < / td >
< td > < p > LFE5U-12, LFE5U-25, LFE5U-45, LFE5U-85, LFE5UM-25, LFE5UM-45, LFE5UM-85, LFE5UM5G-25, LFE5UM5G-45, LFE5UM5G-85< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40" > iCE40< / a > < / p > < / td >
< td > < p > HX1K, HX4K, HX8K, UP5K< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > AS< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2" > MachXO2< / a > < / p > < / td >
< td > < p > 256, 640, 640U, 1200, 1200U, 2000, 2000U, 4000, 7000< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx" > MachXO3D< / a > < / p > < / td >
< td > < p > 4300, 9400< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/lattice.html#lattice" > < span class = "std std-ref" > Lattice< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx" > MachXO3LF< / a > < / p > < / td >
< td > < p > 640, 1300, 2100, 4300, 6900, 9400< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html" > Artix 7< / a > < / p > < / td >
< td > < p > xc7a25t, xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable" > Kintex 7< / a > < / p > < / td >
< td > < p > xc7k70t, xc7k160t, xc7k325t, xc7k410t, xc7k420t, xc7k480t< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html#productTable" > Virtex 7< / a > < / p > < / td >
< td > < p > xc7v585t, xc7v2000t, xc7vx330t, xc7vx415t, xc7vx485t, xc7vx550t, xc7vx690t, xc7vx980t, xc7vx1140t, xc7vh580t, xc7vh870t< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/artix-ultrascale-plus.html" > Artix UltraScale+< / a > < / p > < / td >
< td > < p > xcau15p, xcau25p< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > TBD< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html#productTable" > Kintex UltraScale< / a > < / p > < / td >
< td > < p > xcku035, xcku040, xcku060, xcku115< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK (primary)< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale-plus.html#productTable" > Kintex UltraScale+< / a > < / p > < / td >
< td > < p > xcku3p, xcku5p< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/virtex-6.html" > Virtex 6< / a > < / p > < / td >
< td > < p > xc6vlx130t< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/virtex-ultrascale.html#productTable" > Virtex UltraScale< / a > < / p > < / td >
< td > < p > xcvu095< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > TBD< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html#productTable" > Virtex UltraScale+< / a > < / p > < / td >
< td > < p > xcvu9p< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/spartan-ultrascale-plus.html#productTable" > Spartan UltraScale+< / a > < / p > < / td >
< td > < p > xcsu35p< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > TBD< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html" > Spartan 3< / a > < / p > < / td >
< td > < p > xc3s200, xc3s500e< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html" > Spartan 6< / a > < / p > < / td >
< td > < p > xc6slx9, xc6slx16, xc6slx25, xc6slx45, xc6slx45T, xc6slx150T< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html" > Spartan 7< / a > < / p > < / td >
< td > < p > xc7s15, xc7s25, xc7s50< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf" > XC9500XL< / a > < / p > < / td >
< td > < p > xc9536xl, xc9572xl, xc95144xl, xc95188xl< / p > < / td >
< td > < p > NA< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf" > XC2C/XA2C (coolrunner II)< / a > < / p > < / td >
< td > < p > xc2c32a, xa2c64a< / p > < / td >
< td > < p > TBD< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html" > XCF< / a > < / p > < / td >
< td > < p > xcf01s, xcf02s, xcf04s< / p > < / td >
< td > < p > NA< / p > < / td >
< td > < p > OK< / p > < / td >
< / tr >
< tr class = "row-odd" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html" > Zynq7000< / a > < / p > < / td >
< td > < p > xc7z010, xc7z020< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > NA< / p > < / td >
< / tr >
< tr class = "row-even" > < td > < p > < a class = "reference internal" href = "../vendors/xilinx.html#xilinx" > < span class = "std std-ref" > Xilinx< / span > < / a > < / p > < / td >
< td > < p > < a class = "reference external" href = "https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html" > ZynqMPSoC< / a > < / p > < / td >
< td > < p > xczu2cg, xczu9eg, xczu11eg, xczu17eg< / p > < / td >
< td > < p > OK< / p > < / td >
< td > < p > NA< / p > < / td >
< / tr >
< / tbody >
< / table >
< ul class = "simple" >
< li > < p > IF: Internal Flash< / p > < / li >
< li > < p > AS: Active Serial flash mode< / p > < / li >
< li > < p > NA: Not Available< / p > < / li >
< li > < p > NT: Not Tested< / p > < / li >
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< / section >
< / div >
2026-02-16 11:10:48 +01:00
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