98 lines
3.6 KiB
VHDL
98 lines
3.6 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity xilinx_spiOverJtag is
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port (
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csn : out std_logic;
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sdi_dq0 : out std_logic;
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sdo_dq1 : in std_logic;
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wpn_dq2 : out std_logic;
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hldn_dq3 : out std_logic
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);
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end entity xilinx_spiOverJtag;
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architecture bhv of xilinx_spiOverJtag is
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signal capture, drck, sel, shift, update : std_logic;
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signal runtest : std_logic;
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signal tdi, tdo : std_logic;
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signal fsm_csn : std_logic;
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signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
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begin
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wpn_dq2 <= '1';
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hldn_dq3 <= '1';
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-- jtag -> spi flash
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sdi_dq0 <= tdi;
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tdo <= tdi when (sel) = '0' else sdo_dq1;
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csn <= fsm_csn;
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tmp_cap_s <= capture and sel;
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tmp_up_s <= update and sel;
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tmp_shift_s <= shift and sel;
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process(drck, runtest) begin
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if runtest = '1' then
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fsm_csn <= '1';
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elsif rising_edge(drck) then
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if tmp_cap_s = '1' then
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fsm_csn <= '0';
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elsif tmp_up_s = '1' then
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fsm_csn <= '1';
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else
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fsm_csn <= fsm_csn;
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end if;
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end if;
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end process;
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startupe2_inst : STARTUPE2
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generic map (
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PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
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SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
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)
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port map (
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CFGCLK => open, -- 1-bit output: Configuration main clock output
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CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
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EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
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PREQ => open, -- 1-bit output: PROGRAM request to fabric output
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CLK => '0', -- 1-bit input: User start-up clock input
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GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
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GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
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KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
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PACK => '1', -- 1-bit input: PROGRAM acknowledge input
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USRCCLKO => drck, -- 1-bit input: User CCLK input
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USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
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USRDONEO => '1', -- 1-bit input: User DONE pin output control
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USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output
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);
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bscane2_inst : BSCANE2
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generic map (
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JTAG_CHAIN => 1 -- Value for USER command.
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)
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port map (
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CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller.
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DRCK => drck, -- 1-bit output: Gated TCK output. When SEL
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-- is asserted, DRCK toggles when
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-- CAPTURE or SHIFT are asserted.
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RESET => open, -- 1-bit output: Reset output for TAP controller.
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RUNTEST => runtest, -- 1-bit output: Output asserted when TAP
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-- controller is in Run Test/Idle state.
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SEL => sel, -- 1-bit output: USER instruction active output.
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SHIFT => shift, -- 1-bit output: SHIFT output from TAP controller.
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TCK => open, -- 1-bit output: Test Clock output.
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-- Fabric connection to TAP Clock pin.
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TDI => tdi, -- 1-bit output: Test Data Input (TDI) output
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-- from TAP controller.
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TMS => open, -- 1-bit output: Test Mode Select output.
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-- Fabric connection to TAP.
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UPDATE => update, -- 1-bit output: UPDATE output from TAP controller
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TDO => tdo -- 1-bit input: Test Data Output (TDO) input
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-- for USER function.
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);
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end architecture bhv;
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