2021-06-26 15:24:07 +02:00
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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2019-09-26 18:29:20 +02:00
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#ifndef XILINX_HPP
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#define XILINX_HPP
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2020-04-21 09:08:32 +02:00
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#include <string>
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2021-02-04 07:29:35 +01:00
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#include "configBitstreamParser.hpp"
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2019-09-26 18:29:20 +02:00
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#include "device.hpp"
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2020-03-06 09:05:57 +01:00
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#include "jtag.hpp"
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2020-04-21 09:08:32 +02:00
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#include "spiInterface.hpp"
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2019-09-26 18:29:20 +02:00
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2020-04-21 09:08:32 +02:00
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class Xilinx: public Device, SPIInterface {
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public:
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2020-09-25 18:58:31 +02:00
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Xilinx(Jtag *jtag, const std::string &filename,
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2021-02-21 18:30:13 +01:00
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const std::string &file_type,
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Device::prog_type_t prg_type,
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2021-08-18 15:38:49 +02:00
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const std::string &device_package,
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2021-06-24 18:06:48 +02:00
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bool verify, int8_t verbose);
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2019-09-26 18:29:20 +02:00
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~Xilinx();
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2019-09-28 15:27:58 +02:00
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void program(unsigned int offset = 0) override;
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2021-02-04 07:29:35 +01:00
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void program_spi(ConfigBitstreamParser * bit, unsigned int offset = 0);
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void program_mem(ConfigBitstreamParser *bitfile);
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2021-06-25 11:28:19 +02:00
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bool dumpFlash(const std::string &filename,
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2021-08-18 15:38:49 +02:00
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uint32_t base_addr, uint32_t len) override;
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2020-08-19 16:57:07 +02:00
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int idCode() override;
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void reset() override;
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2020-04-21 09:08:32 +02:00
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2021-08-18 15:38:49 +02:00
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/* -------------- */
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/* xc95 managment */
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/* -------------- */
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/*!
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* \brief enable ISC mode
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*/
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void flow_enable();
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/*!
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* \brief disable ISC mode
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*/
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void flow_disable();
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/*!
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* \brief erase internal flash
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* \return false if something wrong
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*/
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bool flow_erase();
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/*!
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* \brief program internal flash (enable ISC, erase flash,
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* program and disable ISC
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* \return false if something wrong
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*/
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bool flow_program();
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/*!
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* \brief fill a buffer with internal flash content
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* \return buffer filled
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*/
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std::string flow_read();
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2020-04-21 09:08:32 +02:00
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/* spi interface */
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int spi_put(uint8_t cmd, uint8_t *tx, uint8_t *rx,
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2020-08-23 17:16:21 +02:00
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uint32_t len) override;
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int spi_put(uint8_t *tx, uint8_t *rx, uint32_t len) override;
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int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint32_t timeout, bool verbose = false) override;
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private:
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/* list of xilinx family devices */
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enum xilinx_family_t {
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XC95_FAMILY = 0,
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SPARTAN6_FAMILY = 1,
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SPARTAN7_FAMILY = 2,
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ARTIX_FAMILY = 3,
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KINTEX_FAMILY = 4,
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ZYNQ_FAMILY = 5,
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UNKNOWN_FAMILY = 999
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};
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xilinx_family_t _fpga_family; /**< used to store current family */
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2021-06-25 11:28:19 +02:00
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/*!
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* \brief with xilinx devices SPI flash direct access is not possible
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* so a bridge must be loaded in RAM to access flash
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* \return false if missing device mode, true otherwise
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*/
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bool load_bridge();
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std::string _device_package;
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int _xc95_line_len; /**< xc95 only: number of col by flash line */
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};
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#endif
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