openFPGALoader/spiOverJtag/Makefile

XILINX_PARTS := xc3s500evq100 \
	xc6slx9tqg144 xc6slx9csg324 \
	xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
	xc6slx150tfgg484 xc6slx150tcsg484 \
	xc7a25tcpg238 xc7a25tcsg325 \
	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \
	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
	xc7a200tsbg484 xc7a200tfbg484 \
	xc7s25csga225 xc7s25csga324 xc7s50csga324 \
	xc7k160tffg676 \
	xc7k325tffg676 xc7k325tffg900 \
	xc7k420tffg901 \
	xcku5p-ffvb676 \
	xcvu9p-flga2104 xcvu37p-fsvh2892
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

ALTERA_PARTS := 10cl025256 10cl055484 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927
ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))

BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)

all: $(BIT_FILES)

$(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
	gzip -9 -c $< > $@
tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
	./build.py $*

$(ALTERA_BIT_FILES): spiOverJtag_%.rbf.gz: tmp_%/spiOverJtag.rbf
	gzip -9 -c $< > $@
tmp_%/spiOverJtag.rbf: tmp_%/spiOverJtag.sof
	quartus_cpf --option=bitstream_compression=off -c $< $@

tmp_%/spiOverJtag.sof: altera_spiOverJtag.v
	./build.py $*

clean:
	-rm -rf tmp_* *.jou *.log .Xil
Add JTAG to SPI Support on Spartan-6 lx9 CSG324 package. 2023-04-17 06:51:02 +02:00			`XILINX_PARTS := xc3s500evq100 \`
			`xc6slx9tqg144 xc6slx9csg324 \`
			`xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \`
Bitfile and constraints for xc6slx150tcsg484. (#312) 2023-02-16 19:51:04 +01:00			`xc6slx150tfgg484 xc6slx150tcsg484 \`
Add Support for Xilinx Artix-7 a25t (xc7a25t) 2023-04-07 05:28:29 +02:00			`xc7a25tcpg238 xc7a25tcsg325 \`
spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00			`xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \`
add support for colorlight-i9+ board + spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz 2023-06-24 17:02:12 +02:00			`xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \`
spiOverJtag: xc7a100tfgg676 variant 2022-05-10 19:09:21 +02:00			`xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\`
spiOverJtag: Add new package xc7a (fbg484) and xc7a200tfbg484 bitstream Add fbg484 package .xdc constraint file and xc7a200tfbg484 bitstream Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> 2023-02-15 15:26:26 +01:00			`xc7a200tsbg484 xc7a200tfbg484 \`
Add support for xc7s_csga225 and the Digilent CMOD S7 board. 2022-09-30 11:01:49 +02:00			`xc7s25csga225 xc7s25csga324 xc7s50csga324 \`
spiOverJtag: support xc7k160tffg676 2022-05-14 09:30:01 +02:00			`xc7k160tffg676 \`
spiOverJtag: support xc7k420tffg901 2022-05-14 04:38:58 +02:00			`xc7k325tffg676 xc7k325tffg900 \`
Add XCVU9P spiOverJtag bitfile with SPIx8 support 2023-01-21 14:00:20 +01:00			`xc7k420tffg901 \`
Add Support for Xilinx KCU116 (#322) * initial kcu116 support * add kintex ultrascale plus family to xilinx.cpp * add docs * combine xcku and xcvu check * rebuild bitstream for -1 speedgrade 2023-03-09 20:48:19 +01:00			`xcku5p-ffvb676 \`
Add flash support for VCU128 VCU128 does not have secondary flash. 2023-02-20 08:41:48 +01:00			`xcvu9p-flga2104 xcvu37p-fsvh2892`
spiOverJtag: gzip xilinx bitstream 2021-12-19 17:33:39 +01:00			`XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))`
spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00
fix(board): fix missing spiOverJTAG for C10LP-RefKit 2022-12-26 01:36:52 +01:00			`ALTERA_PARTS := 10cl025256 10cl055484 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927`
spiOverJtag: add 5CEBA4F23C8, fix sdc file and compress rbf file 2021-11-28 10:00:21 +01:00			`ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))`
spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00
			`BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)`
add design and bitstream to access SPI through JTAG 2019-10-05 19:03:28 +02:00
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings. 2020-08-08 11:42:38 +02:00			`all: $(BIT_FILES)`

spiOverJtag: gzip xilinx bitstream 2021-12-19 17:33:39 +01:00			`$(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit`
			`gzip -9 -c $< > $@`
spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00			`tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v`
			`./build.py $*`

spiOverJtag: add 5CEBA4F23C8, fix sdc file and compress rbf file 2021-11-28 10:00:21 +01:00			`$(ALTERA_BIT_FILES): spiOverJtag_%.rbf.gz: tmp_%/spiOverJtag.rbf`
			`gzip -9 -c $< > $@`
			`tmp_%/spiOverJtag.rbf: tmp_%/spiOverJtag.sof`
spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00			`quartus_cpf --option=bitstream_compression=off -c $< $@`

			`tmp_%/spiOverJtag.sof: altera_spiOverJtag.v`
			`./build.py $*`
add design and bitstream to access SPI through JTAG 2019-10-05 19:03:28 +02:00
			`clean:`
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings. 2020-08-08 11:42:38 +02:00			`-rm -rf tmp_* .jou .log .Xil`