2019-10-05 19:00:10 +02:00
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/*
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* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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2020-08-23 17:14:21 +02:00
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#include <string.h>
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2019-10-05 19:00:10 +02:00
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#include <stdlib.h>
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#include <unistd.h>
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#include <iostream>
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#include "ftdipp_mpsse.hpp"
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#include "progressBar.hpp"
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#include "spiFlash.hpp"
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2020-04-21 09:00:57 +02:00
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#include "spiInterface.hpp"
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2019-10-05 19:00:10 +02:00
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/* read/write status register : 0B addr + 0 dummy */
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2020-04-21 09:00:57 +02:00
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#define FLASH_WRSR 0x01
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#define FLASH_RDSR 0x05
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2019-10-05 19:00:10 +02:00
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# define FLASH_RDSR_WIP (0x01)
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# define FLASH_RDSR_WEL (0x02)
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/* flash program */
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#define FLASH_PP 0x02
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/* write [en|dis]able : 0B addr + 0 dummy */
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2020-04-21 09:00:57 +02:00
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#define FLASH_WRDIS 0x04
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#define FLASH_WREN 0x06
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2019-10-05 19:00:10 +02:00
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/* Read OTP : 3 B addr + 8 clk cycle*/
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2020-04-21 09:00:57 +02:00
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#define FLASH_ROTP 0x4B
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#define FLASH_POWER_UP 0xAB
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#define FLASH_POWER_DOWN 0xB9
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2019-10-05 19:00:10 +02:00
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/* read/write non volatile register: 0B addr + 0 dummy */
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#define FLASH_RDNVCR 0xB5
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2020-08-23 17:14:21 +02:00
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#define FLASH_WRNVCR 0xB1
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/* read/write volatile register */
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#define FLASH_RDVCR 0x85
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#define FLASH_WRVCR 0x81
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2019-10-05 19:00:10 +02:00
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/* bulk erase */
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#define FLASH_BE 0xC7
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/* sector (64kb) erase */
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#define FLASH_SE 0xD8
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/* read/write lock register : 3B addr + 0 dummy */
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#define FLASH_WRLR 0xE5
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#define FLASH_RDLR 0xE8
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/* read/clear flag status register : 0B addr + 0 dummy */
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#define FLASH_CLFSR 0x50
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#define FLASH_RFSR 0x70
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/* */
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#define FLASH_WRVECR 0x61
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#define FLASH_RDVECR 0x65
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2021-01-30 07:57:49 +01:00
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SPIFlash::SPIFlash(SPIInterface *spi, int8_t verbose):_spi(spi), _verbose(verbose)
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2019-10-05 19:00:10 +02:00
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{
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}
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int SPIFlash::bulk_erase()
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{
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if (write_enable() == -1)
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return -1;
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_BE, NULL, NULL, 0);
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return _spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WIP, 0x00, 100000, true);
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2019-10-05 19:00:10 +02:00
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}
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int SPIFlash::sector_erase(int addr)
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{
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2020-08-23 17:14:21 +02:00
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uint8_t tx[4];
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tx[0] = (uint8_t)(FLASH_SE );
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tx[1] = (uint8_t)(0xff & (addr >> 16));
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tx[2] = (uint8_t)(0xff & (addr >> 8));
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tx[3] = (uint8_t)(0xff & (addr ));
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_spi->spi_put(tx, NULL, 4);
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2019-10-05 19:00:10 +02:00
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return 0;
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}
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int SPIFlash::sectors_erase(int base_addr, int size)
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{
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2021-01-30 07:57:49 +01:00
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int ret = 0;
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2019-10-05 19:00:10 +02:00
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int start_addr = base_addr;
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2020-08-23 17:14:21 +02:00
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int end_addr = (base_addr + size + 0xffff) & ~0xffff;
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2021-01-30 07:57:49 +01:00
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ProgressBar progress("Erasing", end_addr, 50, _verbose < 0);
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2019-10-05 19:00:10 +02:00
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for (int addr = start_addr; addr < end_addr; addr += 0x10000) {
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2021-01-30 07:57:49 +01:00
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if (write_enable() == -1) {
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ret = -1;
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break;
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}
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if (sector_erase(addr) == -1) {
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ret = -1;
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break;
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}
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if (_spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WIP, 0x00, 100000, false) == -1) {
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ret = -1;
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break;
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}
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2019-10-05 19:00:10 +02:00
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progress.display(addr);
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}
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2021-01-30 07:57:49 +01:00
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if (ret == 0)
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progress.done();
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else
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progress.fail();
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return ret;
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2019-10-05 19:00:10 +02:00
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}
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2020-03-15 08:22:29 +01:00
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int SPIFlash::write_page(int addr, uint8_t *data, int len)
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2019-10-05 19:00:10 +02:00
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{
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2020-03-15 08:22:29 +01:00
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uint8_t tx[len+3];
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tx[0] = (uint8_t)(0xff & (addr >> 16));
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2020-08-23 17:14:21 +02:00
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tx[1] = (uint8_t)(0xff & (addr >> 8));
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tx[2] = (uint8_t)(0xff & (addr ));
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memcpy(tx+3, data, len);
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2019-10-05 19:00:10 +02:00
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if (write_enable() == -1)
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return -1;
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_PP, tx, NULL, len+3);
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return _spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WIP, 0x00, 1000);
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2019-10-05 19:00:10 +02:00
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}
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2020-08-23 17:14:21 +02:00
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int SPIFlash::read(int base_addr, uint8_t *data, int len)
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{
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uint8_t tx[len+3];
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uint8_t rx[len+3];
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tx[0] = (uint8_t)(0xff & (base_addr >> 16));
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tx[1] = (uint8_t)(0xff & (base_addr >> 8));
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tx[2] = (uint8_t)(0xff & (base_addr ));
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int ret = _spi->spi_put(0x03, tx, rx, len+3);
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if (ret == 0)
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memcpy(data, rx+3, len);
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else
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printf("error\n");
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return ret;
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}
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2019-10-05 19:00:10 +02:00
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int SPIFlash::erase_and_prog(int base_addr, uint8_t *data, int len)
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{
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2020-04-21 19:25:35 +02:00
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/* check Block Protect Bits */
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uint8_t status = read_status_reg();
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if ((status & 0x1c) !=0) {
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if (write_enable() != 0)
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return -1;
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if (disable_protection() != 0)
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return -1;
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}
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2021-01-30 07:57:49 +01:00
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ProgressBar progress("Writing", len, 50, _verbose < 0);
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2020-08-23 17:14:21 +02:00
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if (sectors_erase(base_addr, len) == -1)
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2019-10-05 19:00:10 +02:00
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return -1;
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2020-04-21 09:00:57 +02:00
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2019-10-05 19:00:10 +02:00
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uint8_t *ptr = data;
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int size = 0;
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2020-08-23 17:14:21 +02:00
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for (int addr = 0; addr < len; addr += size, ptr+=size) {
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2019-10-05 19:00:10 +02:00
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size = (addr + 256 > len)?(len-addr) : 256;
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2020-08-23 17:14:21 +02:00
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if (write_page(base_addr + addr, ptr, size) == -1)
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2019-10-05 19:00:10 +02:00
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return -1;
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progress.display(addr);
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}
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progress.done();
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return 0;
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}
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void SPIFlash::reset()
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{
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2020-08-23 17:14:21 +02:00
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uint8_t data[8];
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memset(data, 0xff, 8);
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(0xff, data, NULL, 8);
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2019-10-05 19:00:10 +02:00
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}
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void SPIFlash::read_id()
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{
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int len = 4;
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uint8_t rx[512];
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2020-04-21 09:02:48 +02:00
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bool has_edid = false;
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2019-10-05 19:00:10 +02:00
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(0x9F, NULL, rx, 4);
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2019-10-05 19:00:10 +02:00
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int d = 0;
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for (int i=0; i < 4; i++) {
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d = d << 8;
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d |= (0x00ff & (int)rx[i]);
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0)
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2019-11-21 09:19:48 +01:00
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printf("%x ", rx[i]);
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2019-10-05 19:00:10 +02:00
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}
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0)
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2019-11-21 09:19:48 +01:00
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printf("read %x\n", d);
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2019-10-05 19:00:10 +02:00
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2020-04-21 09:02:48 +02:00
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/* read extented */
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if ((d & 0xff) != 0) {
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has_edid = true;
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len += (d & 0x0ff);
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_spi->spi_put(0x9F, NULL, rx, len);
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}
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2019-10-05 19:00:10 +02:00
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/* must be 0x20BA1810 ... */
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printf("Detail: \n");
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printf("Jedec ID : %02x\n", rx[0]);
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printf("memory type : %02x\n", rx[1]);
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printf("memory capacity : %02x\n", rx[2]);
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2020-04-21 09:02:48 +02:00
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if (has_edid) {
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printf("EDID + CFD length : %02x\n", rx[3]);
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printf("EDID : %02x%02x\n", rx[5], rx[4]);
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printf("CFD : ");
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0) {
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2020-04-21 09:02:48 +02:00
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for (int i = 6; i < len; i++)
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printf("%02x ", rx[i]);
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printf("\n");
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} else {
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printf("\n");
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}
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2019-11-21 09:19:48 +01:00
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}
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2019-10-05 19:00:10 +02:00
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}
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2019-11-21 09:19:48 +01:00
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uint8_t SPIFlash::read_status_reg()
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2019-10-05 19:00:10 +02:00
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{
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uint8_t rx;
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_RDSR, NULL, &rx, 1);
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0) {
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2019-10-05 19:00:10 +02:00
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printf("RDSR : %02x\n", rx);
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printf("WIP : %d\n", rx&0x01);
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printf("WEL : %d\n", (rx>>1)&0x01);
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printf("BP : %x\n", (((rx>>6)&0x01)<<3) | ((rx >> 2) & 0x07));
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printf("TB : %d\n", (((rx>>5)&0x01)));
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printf("SRWD : %d\n", (((rx>>7)&0x01)));
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}
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return rx;
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}
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2020-08-23 17:14:21 +02:00
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uint16_t SPIFlash::readNonVolatileCfgReg()
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{
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uint8_t rx[2];
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_spi->spi_put(FLASH_RDNVCR, NULL, rx, 2);
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0)
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2020-08-23 17:14:21 +02:00
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printf("Non Volatile %x %x\n", rx[0], rx[1]);
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return (rx[1] << 8) | rx[0];
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}
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uint16_t SPIFlash::readVolatileCfgReg()
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{
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uint8_t rx[2];
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_spi->spi_put(FLASH_RDVCR, NULL, rx, 2);
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2021-01-30 07:57:49 +01:00
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if (_verbose > 0)
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2020-08-23 17:14:21 +02:00
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printf("Volatile %x %x\n", rx[0], rx[1]);
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return (rx[1] << 8) | rx[0];
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}
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2019-10-05 19:00:10 +02:00
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void SPIFlash::power_up()
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{
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_POWER_UP, NULL, NULL, 0);
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2019-10-05 19:00:10 +02:00
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}
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void SPIFlash::power_down()
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{
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_POWER_DOWN, NULL, NULL, 0);
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2019-10-05 19:00:10 +02:00
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}
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2019-11-21 09:19:48 +01:00
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int SPIFlash::write_enable()
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2019-10-05 19:00:10 +02:00
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{
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2020-04-21 09:00:57 +02:00
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_spi->spi_put(FLASH_WREN, NULL, NULL, 0);
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2019-10-05 19:00:10 +02:00
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/* wait WEL */
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2020-04-21 09:00:57 +02:00
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if (_spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WEL, FLASH_RDSR_WEL, 1000)) {
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2019-10-05 19:00:10 +02:00
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printf("write en: Error\n");
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|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int SPIFlash::write_disable()
|
|
|
|
|
{
|
2020-04-21 09:00:57 +02:00
|
|
|
_spi->spi_put(FLASH_WRDIS, NULL, NULL, 0);
|
2019-10-05 19:00:10 +02:00
|
|
|
/* wait ! WEL */
|
2020-04-21 09:00:57 +02:00
|
|
|
int ret = _spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WEL, 0x00, 1000);
|
2019-10-05 19:00:10 +02:00
|
|
|
if (ret == -1)
|
|
|
|
|
printf("write disable: Error\n");
|
2021-01-30 07:57:49 +01:00
|
|
|
else if (_verbose > 0)
|
2019-10-05 19:00:10 +02:00
|
|
|
printf("write disable: Success\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int SPIFlash::disable_protection()
|
|
|
|
|
{
|
|
|
|
|
uint8_t data = 0x00;
|
2020-04-21 09:00:57 +02:00
|
|
|
_spi->spi_put(FLASH_WRSR, &data, NULL, 1);
|
|
|
|
|
if (_spi->spi_wait(FLASH_RDSR, 0xff, 0, 1000) < 0)
|
2019-10-05 19:00:10 +02:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
/* read status */
|
|
|
|
|
if (read_status_reg() != 0) {
|
|
|
|
|
std::cout << "disable protection failed" << std::endl;
|
|
|
|
|
return -1;
|
|
|
|
|
} else
|
|
|
|
|
return 0;
|
|
|
|
|
}
|