mirror of
https://git.code.sf.net/p/ngspice/ngspice
synced 2026-09-02 10:47:20 +02:00
Brian Taylor
d881158a41
running in parallel on a multi-core machine (12 min execution time on a i9 9900, ngspice compiled with gcc, debug mode enabled. Linux with Valgrind and Parallel are required.
73 lines
1.7 KiB
Plaintext
73 lines
1.7 KiB
Plaintext
* sw like an NMOS inverter with resistive load
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.subckt invertern In Out VDD DGND
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*sp out vdd in vdd swswitch on
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Rl out vdd 10k
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Cl out dgnd 0.1p
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*C2 out vdd 0.1p
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sn out dgnd in dgnd swswitch off
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.ends invertern
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* sw like a PMOS inverter with resistive load
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.subckt inverterp In Out VDD DGND
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sp out vdd vdd in swswitch
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Rl out 0 10k
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*Cl out dgnd 0.1p
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C2 out vdd 0.1p
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*sn out dgnd in dgnd swswitch off
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.ends inverterp
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* sw like a CMOS inverter
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.subckt inverter In Out VDD DGND
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sp out vdd vdd in swswitch
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Rin in 0 1e9
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Cl out dgnd 0.1p
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C2 out vdd 0.1p
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sn out dgnd in dgnd swswitch
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.ends inverter
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.model swswitch sw (vt=1 vh=0.1 ron=1k roff=1e12)
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.model switchn sw (vt=1 vh=0.1 ron=1k roff=1e12)
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* sw like a CMOS inverter with PSPICE VSWITCH
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.subckt invertervs In Out VDD DGND
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sp out vdd vdd in swn
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Rin in 0 1e9
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Cl out dgnd 0.1p
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C2 out vdd 0.1p
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sn out dgnd in dgnd swn
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.ends invertervs
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.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 )
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* sw like a CMOS inverter with PSPICE VSWITCH
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.subckt invertervs2 In Out VDD DGND
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sp out vdd vdd in swn
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Rin in 0 1e9
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Cl out dgnd 0.1p
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C2 out vdd 0.1p
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sn out dgnd in dgnd swn
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.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 )
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.ends invertervs2
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* sw like a CMOS inverter with PSPICE VSWITCH
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.subckt invertervs3 In Out VDD DGND
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sp out vdd vdd in swn2
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Rin in 0 1e9
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Cl out dgnd 0.1p
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C2 out vdd 0.1p
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sn out dgnd in dgnd swn2
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.ends invertervs3
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.MODEL SWN2 VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 )
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* sw like a CMOS inverter with PSPICE VSWITCH
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.subckt invertervs4 In Out VDD DGND
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sp out vdd vdd in swn
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Rin in 0 1e9
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Cl out dgnd 0.1p
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C2 out vdd 0.1p
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sn out dgnd in dgnd swn
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.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=2k ROFF=1e12 )
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.ends invertervs4
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