dwarning 2c7f1e471b vbic: rm obsolete regression test		2024-05-01 10:34:01 +02:00
..
Monte_Carlo	…
TransImpedanceAmp	…
TransmissionLines	Better visibility of the results	2023-07-15 11:11:48 +02:00
adms	…
cider	When Cider models are present, a normal batch mode sp_shutdown (for example, ngspice -b cmosinv.cir) will call com_quit(NULL). This cleans up so that valgrind will find no leaks in Cider devices after sp_shutdown. To disable this feature, set the environment variable CIDER_COM_QUIT="OFF". Even though it really does not matter that Cider memory is cleared just before exit, it makes it cleaner for valgrind checks.	2023-07-15 11:32:37 +02:00
control_structs	…
ddt	…
digital	Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE.	2023-07-31 14:27:59 +02:00
hicum2	…
inductive-systems	…
klu/Circuits	Added missing ISCAS85 libraries	2023-08-16 11:14:18 +02:00
loops	Repeat loop requires plain number, transformed vector, or transformed variable	2024-03-19 17:05:10 +01:00
measure	measure example with expression evaluation	2024-03-29 17:12:40 +01:00
memristor	…
mos	MOS example files updated and moved to its own directory	2023-01-24 15:17:31 +01:00
noise	implement osdi noise support	2023-11-04 19:36:30 +01:00
numparam	…
optran	…
osdi	add examples for OSDI noise	2023-11-04 19:36:30 +01:00
p-to-n-examples	Use sparse, as KLU will fail.	2023-09-10 13:43:09 +02:00
paranoia	Fix some typos.	2023-12-18 20:13:06 +01:00
plot	…
probe	…
proc2mod	…
pss	…
snapshot	…
soa	Add a comment to say that LT/PSPICE compatability is needed.	2023-07-31 14:29:50 +02:00
soi	…
sp	better visibility	2023-07-31 14:30:37 +02:00
svg	…
tclspice	…
transient-noise	…
utf-8/стекло	…
various	Add a transformer with parameters on the .subckt line	2024-01-24 10:11:44 +01:00
vbic	vbic: rm obsolete regression test	2024-05-01 10:34:01 +02:00
vdmos	Add vto model parameter (the default has changed!), add .ic	2023-05-27 10:47:43 +02:00
xspice	Add the support files for co-simulation with Verilog code	2023-11-27 20:55:59 +00:00