702 lines
25 KiB
Perl
702 lines
25 KiB
Perl
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#
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# hspice DC, AC and noise test routines
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#
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#
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# Rel Date Who Comments
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# ==== ========== ============= ========
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# 1.4 04/06/11 Geoffrey Coram Fixed version detection; fixed ac-freq result printing
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# 1.3 06/21/07 Rob Jones Verilog-A model support added
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# HSPICE version detection updated
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# 1.2 06/30/06 Colin McAndrew/ Floating node support added
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# Rob Jones Noise simulation added
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# HSPICE version detection improved
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# 1.0 04/13/06 Colin McAndrew Initial version
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#
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package simulate;
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if (defined($main::simulatorCommand)) {
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$simulatorCommand=$main::simulatorCommand;
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} else {
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$simulatorCommand="hspice";
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}
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$netlistFile="hspiceCkt";
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use strict;
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sub version {
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my($version,$vaVersion);
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$version="unknown";
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$vaVersion="unknown";
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if (!open(OF,">$simulate::netlistFile")) {
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die("ERROR: cannot open file $simulate::netlistFile, stopped");
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}
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print OF "";
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print OF "r1 1 0 1";
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print OF "v1 1 0 1";
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print OF ".op";
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print OF ".end";
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close(OF);
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if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null|")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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while (<SIMULATE>) {
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chomp;
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if (s/.+HSPICE\s+-*\s*//) {
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($version=$_)=~s/\s+.*//;
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last;
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}
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}
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close(SIMULATE);
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if (! $main::debug) {
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unlink($simulate::netlistFile);
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unlink("$simulate::netlistFile.st0");
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if (defined($main::verilogaFile)) {
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unlink("$simulate::netlistFile.val");
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}
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if (!opendir(DIRQA,".")) {
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die("ERROR: cannot open directory ., stopped");
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}
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foreach (grep(/^$simulate::netlistFile\.ic/,readdir(DIRQA))) {unlink($_)}
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closedir(DIRQA);
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unlink("hspice.errors");
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unlink("simout.tmp");
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}
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return($version,$vaVersion);
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}
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sub runNoiseTest {
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my($variant,$outputFile)=@_;
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my($arg,$name,$value,$type,$pin,$noisePin);
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my(@BiasList,$i,@Field);
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my(@X,@Noise,$temperature,$biasVoltage,$sweepVoltage,$inData);
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#
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# Make up the netlist, using a subckt to encapsulate the
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# instance. This simplifies handling of the variants as
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# the actual instance is driven by voltage-controlled
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# voltage sources from the subckt pins, and the currents
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# are fed back to the subckt pins using current-controlled
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# current sources. Pin swapping, polarity reversal, and
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# m-factor scaling can all be handled by simple modifications
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# of this subckt.
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#
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@X=();@Noise=();
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$noisePin=$main::Outputs[0];
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foreach $temperature (@main::Temperature) {
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foreach $biasVoltage (split(/\s+/,$main::biasListSpec)) {
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if ($main::fMin == $main::fMax) {
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push(@X,@main::BiasSweepList);
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}
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foreach $sweepVoltage (@main::BiasSweepList) {
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if (!open(OF,">$simulate::netlistFile")) {
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die("ERROR: cannot open file $simulate::netlistFile, stopped");
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}
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print OF "* Noise simulation for $main::simulatorName";
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&generateCommonNetlistInfo($variant,$temperature);
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print OF "vin dummy 0 0 ac 1";
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print OF "rin dummy 0 rmod";
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print OF ".model rmod r res=1 noise=0";
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foreach $pin (@main::Pin) {
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if ($main::isFloatingPin{$pin}) {
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print OF "i_$pin $pin 0 0";
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} elsif ($pin eq $main::biasListPin) {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $biasVoltage";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_$pin $pin 0 $biasVoltage";
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}
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} elsif ($pin eq $main::biasSweepPin) {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $sweepVoltage";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_$pin $pin 0 $sweepVoltage";
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}
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} else {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $main::BiasFor{$pin}";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_${pin} ${pin} 0 $main::BiasFor{$pin}";
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}
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}
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}
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print OF "x1 ".join(" ",@main::Pin)." mysub";
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if ($main::outputNoise == 2) {
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print OF ".ac $main::frequencySpec";
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print OF ".noise v($noisePin,$main::Outputs[1]) vin";
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} else {
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if (! $main::isFloatingPin{$noisePin}) {
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print OF "fn 0 n_$noisePin v_$noisePin 1";
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print OF "rn 0 n_$noisePin rmod";
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}
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print OF ".ac $main::frequencySpec";
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if ($main::isFloatingPin{$noisePin}) {
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print OF ".noise v($noisePin) vin";
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} else {
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print OF ".noise v(n_$noisePin) vin";
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}
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}
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print OF ".print noise onoise";
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print OF ".end";
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close(OF);
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#
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# Run simulations and get the results
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#
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if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null|")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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$inData=0;
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;@Field=split;
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if (/freq\s+onoise/i) {$inData=1;<SIMULATE>;next}
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if ($#Field != 1) {$inData=0;}
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next if (!$inData);
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if ($main::fMin != $main::fMax) {
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push(@X,&modelQa::unScale($Field[0]));
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}
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push(@Noise,(&modelQa::unScale($Field[1]))**2);
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}
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close(SIMULATE);
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}
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}
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}
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#
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# Write the results to a file
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#
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if (!open(OF,">$outputFile")) {
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die("ERROR: cannot open file $outputFile, stopped");
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}
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if ($main::fMin == $main::fMax) {
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printf OF ("V($main::biasSweepPin)");
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} else {
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printf OF ("Freq");
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}
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if ($main::outputNoise == 2) {
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print OF (" N($noisePin,$main::Outputs[1])");
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} else {
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print OF (" N($noisePin)");
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}
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for ($i=0;$i<=$#X;++$i) {
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if (defined($Noise[$i])) {printf OF ("$X[$i] $Noise[$i]\n")}
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}
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close(OF);
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#
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# Clean up, unless the debug flag was specified
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#
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if (! $main::debug) {
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unlink($simulate::netlistFile);
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unlink("$simulate::netlistFile.st0");
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if (defined($main::verilogaFile)) {
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unlink("$simulate::netlistFile.val");
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}
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if (!opendir(DIRQA,".")) {
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die("ERROR: cannot open directory ., stopped");
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}
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foreach (grep(/^$simulate::netlistFile\.ic/,readdir(DIRQA))) {unlink($_)}
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closedir(DIRQA);
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}
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}
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sub runAcTest {
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my($variant,$outputFile)=@_;
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my($arg,$name,$value,$type,$pin,$mPin,$fPin,%NextPin,%PrevPin,$first_fPin);
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my(@BiasList,$i,$j,@Field);
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my(@X,$omega,%g,%c,%q,$twoPi,$temperature,$biasVoltage,$sweepVoltage);
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my($inData,$inResults,$outputLine);
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$twoPi=8.0*atan2(1.0,1.0);
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#
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# Make up the netlist, using a subckt to encapsulate the
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# instance. This simplifies handling of the variants as
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# the actual instance is driven by voltage-controlled
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# voltage sources from the subckt pins, and the currents
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# are fed back to the subckt pins using current-controlled
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# current sources. Pin swapping, polarity reversal, and
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# m-factor scaling can all be handled by simple modifications
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# of this subckt.
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#
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foreach $mPin (@main::Pin) {
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if ($main::needAcStimulusFor{$mPin}) {
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$first_fPin=$mPin;
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last;
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}
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}
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if (!open(OF,">$simulate::netlistFile")) {
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die("ERROR: cannot open file $simulate::netlistFile, stopped");
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}
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print OF "* AC simulation for $main::simulatorName";
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&generateCommonNetlistInfo($variant,$main::Temperature[0]);
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@BiasList=split(/\s+/,$main::biasListSpec);
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print OF ".param vbias=$BiasList[0]";
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print OF ".param vsweep=$main::BiasSweepList[0]";
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foreach $pin (@main::Pin) {
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if ($pin eq $first_fPin) {
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print OF ".param ac_$pin=1";
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} else {
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print OF ".param ac_$pin=0";
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}
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if ($main::isFloatingPin{$pin}) {
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print OF "i_$pin $pin 0 0";
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} elsif ($pin eq $main::biasListPin) {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} vbias ac ac_$pin";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_${pin} ${pin} 0 vbias ac ac_$pin";
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}
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} elsif ($pin eq $main::biasSweepPin) {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} vsweep ac ac_$pin";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_${pin} ${pin} 0 vsweep ac ac_$pin";
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}
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} else {
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if (defined($main::referencePinFor{$pin})) {
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print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $main::BiasFor{$pin} ac ac_$pin";
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print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
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} else {
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print OF "v_${pin} ${pin} 0 $main::BiasFor{$pin} ac ac_$pin";
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}
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}
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}
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print OF "x1 ".join(" ",@main::Pin)." mysub";
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print OF ".ac $main::frequencySpec";
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foreach $pin (@main::Pin) {print OF ".print ac ir(v_$pin) ii(v_$pin)"}
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for ($i=0;$i<=$#main::Pin;++$i) {
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next if (!$main::needAcStimulusFor{$main::Pin[$i]});
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$j=$i;
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while (1) {
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--$j;
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$j=$#main::Pin if ($j < 0);
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if ($main::needAcStimulusFor{$main::Pin[$j]}) {
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$PrevPin{$main::Pin[$i]}=$main::Pin[$j];
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last;
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}
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}
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}
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foreach $temperature (@main::Temperature) {
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foreach $biasVoltage (@BiasList) {
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foreach $sweepVoltage (@main::BiasSweepList) {
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foreach $pin (@main::Pin) {
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next if (!$main::needAcStimulusFor{$pin});
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next if ($temperature == $main::Temperature[0] && $biasVoltage == $BiasList[0]
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&& $sweepVoltage == $main::BiasSweepList[0] && $pin eq $first_fPin);
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print OF ".alter";
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if ($biasVoltage == $BiasList[0] && $sweepVoltage == $main::BiasSweepList[0] && $pin eq $first_fPin) {
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print OF ".temp $temperature";
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}
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if ($sweepVoltage == $main::BiasSweepList[0] && $pin eq $main::Pin[0]) {
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print OF ".param vbias=$biasVoltage";
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}
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if ($pin eq $first_fPin) {
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print OF ".param vsweep=$sweepVoltage";
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}
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print OF ".param ac_$PrevPin{$pin}=0";
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print OF ".param ac_$pin=1";
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}
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}
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}
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}
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print OF ".end";
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close(OF);
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#
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# Run simulations and get the results
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#
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foreach $mPin (@main::Pin) {
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foreach $fPin (@main::Pin) {
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@{$g{$mPin,$fPin}}=();
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@{$c{$mPin,$fPin}}=();
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@{$q{$mPin,$fPin}}=();
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}
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}
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for ($i=0;$i<=$#main::Pin;++$i) {
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next if (!$main::needAcStimulusFor{$main::Pin[$i]});
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$j=$i;
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while (1) {
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++$j;
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$j=0 if ($j > $#main::Pin);
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if ($main::needAcStimulusFor{$main::Pin[$j]}) {
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$NextPin{$main::Pin[$i]}=$main::Pin[$j];
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last;
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}
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}
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}
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if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null|")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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$inData=0;$inResults=0;
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if ($main::fMin == $main::fMax) {
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@X=();
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foreach $temperature (@main::Temperature) {
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foreach $biasVoltage (split(/\s+/,$main::biasListSpec)) {
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push(@X,@main::BiasSweepList);
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}
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}
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}
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$fPin=$first_fPin;
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while (<SIMULATE>) {
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chomp;
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if (/ac\s+analysis/i && /temp=/i) {$inResults=1;$inData=0;next}
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if (/info/i && /job\s+concluded/) {$inResults=0;$fPin=$NextPin{$fPin}}
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next if (!$inResults);
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s/^\s+//;s/\s+$//;
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if (/^v_([a-zA-z][a-zA-Z0-9]*)/) {$mPin=$1;$inData=1;next;}
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@Field=split;
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if ($#Field != 2
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|| &modelQa::unScale($Field[0]) !~ /^($main::number)$/
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|| &modelQa::unScale($Field[1]) !~ /^($main::number)$/
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|| &modelQa::unScale($Field[2]) !~ /^($main::number)$/) {
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$inData=0;
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next;
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}
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next if (! $inData);
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if (($main::fMin != $main::fMax) && ($fPin eq $first_fPin)) {
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push(@X,&modelQa::unScale($Field[0]));
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}
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$omega=$twoPi*&modelQa::unScale($Field[0]);
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push(@{$g{$mPin,$fPin}},&modelQa::unScale($Field[1]));
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if ($mPin eq $fPin) {
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push(@{$c{$mPin,$fPin}},&modelQa::unScale($Field[2])/$omega);
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} else {
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push(@{$c{$mPin,$fPin}},-1*&modelQa::unScale($Field[2])/$omega);
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}
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if (abs(&modelQa::unScale($Field[1])) > 1.0e-99) {
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push(@{$q{$mPin,$fPin}},&modelQa::unScale($Field[2])/&modelQa::unScale($Field[1]));
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} else {
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push(@{$q{$mPin,$fPin}},1.0e99);
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}
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}
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close(SIMULATE);
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#
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# Write the results to a file
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#
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if (!open(OF,">$outputFile")) {
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die("ERROR: cannot open file $outputFile, stopped");
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}
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if ($main::fMin == $main::fMax) {
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printf OF ("V($main::biasSweepPin)");
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} else {
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printf OF ("Freq");
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}
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foreach (@main::Outputs) {
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($type,$mPin,$fPin)=split(/\s+/,$_);
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printf OF (" $type($mPin,$fPin)");
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}
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printf OF ("\n");
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for ($i=0;$i<=$#X;++$i) {
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$outputLine="$X[$i]";
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foreach (@main::Outputs) {
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($type,$mPin,$fPin)=split(/\s+/,$_);
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if ($type eq "g") {
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if (defined(${$g{$mPin,$fPin}}[$i])) {
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$outputLine.=" ${$g{$mPin,$fPin}}[$i]";
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} else {
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undef($outputLine);last;
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}
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} elsif ($type eq "c") {
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if (defined(${$c{$mPin,$fPin}}[$i])) {
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$outputLine.=" ${$c{$mPin,$fPin}}[$i]";
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} else {
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undef($outputLine);last;
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}
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} else {
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if (defined(${$q{$mPin,$fPin}}[$i])) {
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$outputLine.=" ${$q{$mPin,$fPin}}[$i]";
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} else {
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undef($outputLine);last;
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}
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}
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}
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if (defined($outputLine)) {printf OF ("$outputLine\n")}
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}
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close(OF);
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#
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# Clean up, unless the debug flag was specified
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#
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if (! $main::debug) {
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unlink($simulate::netlistFile);
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unlink("$simulate::netlistFile.st0");
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if (defined($main::verilogaFile)) {
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unlink("$simulate::netlistFile.val");
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}
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if (!opendir(DIRQA,".")) {
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die("ERROR: cannot open directory ., stopped");
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}
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foreach (grep(/^$simulate::netlistFile\.ic/,readdir(DIRQA))) {unlink($_)}
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closedir(DIRQA);
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unlink("hspice.errors");
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unlink("simout.tmp");
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}
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}
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sub runDcTest {
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my($variant,$outputFile)=@_;
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my($arg,$name,$value,$i,$pin,@Field);
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my(@BiasList,$start,$stop,$step);
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my(@V,%DC,$temperature,$biasVoltage);
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my($inData,$inResults);
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#
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# Make up the netlist, using a subckt to encapsulate the
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# instance. This simplifies handling of the variants as
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# the actual instance is driven by voltage-controlled
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# voltage sources from the subckt pins, and the currents
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|
# are fed back to the subckt pins using current-controlled
|
|
# current sources. Pin swapping, polarity reversal, and
|
|
# m-factor scaling can all be handled by simple modifications
|
|
# of this subckt.
|
|
#
|
|
|
|
if (!open(OF,">$simulate::netlistFile")) {
|
|
die("ERROR: cannot open file $simulate::netlistFile, stopped");
|
|
}
|
|
print OF "* DC simulation for $main::simulatorName";
|
|
&generateCommonNetlistInfo($variant,$main::Temperature[0]);
|
|
@BiasList=split(/\s+/,$main::biasListSpec);
|
|
($start,$stop,$step)=split(/\s+/,$main::biasSweepSpec);
|
|
$start-=$step;
|
|
print OF ".param vbias=$BiasList[0]";
|
|
foreach $pin (@main::Pin) {
|
|
if ($main::isFloatingPin{$pin}) {
|
|
print OF "i_$pin $pin 0 0";
|
|
} elsif ($pin eq $main::biasListPin) {
|
|
if (defined($main::referencePinFor{$pin})) {
|
|
print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} vbias";
|
|
print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
|
|
} else {
|
|
print OF "v_${pin} ${pin} 0 vbias";
|
|
}
|
|
} elsif ($pin eq $main::biasSweepPin) {
|
|
if (defined($main::referencePinFor{$pin})) {
|
|
print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $start";
|
|
print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
|
|
} else {
|
|
print OF "v_${pin} ${pin} 0 $start";
|
|
}
|
|
} else {
|
|
if (defined($main::referencePinFor{$pin})) {
|
|
print OF "v_${pin} ${pin} ${pin}_$main::referencePinFor{$pin} $main::BiasFor{$pin}";
|
|
print OF "e_${pin} ${pin}_$main::referencePinFor{$pin} 0 $main::referencePinFor{$pin} 0 1";
|
|
} else {
|
|
print OF "v_${pin} ${pin} 0 $main::BiasFor{$pin}";
|
|
}
|
|
}
|
|
}
|
|
print OF "x1 ".join(" ",@main::Pin)." mysub";
|
|
print OF ".dc v_$main::biasSweepPin $main::biasSweepSpec";
|
|
foreach $pin (@main::Outputs) {
|
|
if ($main::isFloatingPin{$pin}) {
|
|
print OF ".print v($pin)"
|
|
} else {
|
|
print OF ".print i(v_$pin)"
|
|
}
|
|
}
|
|
foreach $temperature (@main::Temperature) {
|
|
foreach $biasVoltage (@BiasList) {
|
|
next if ($temperature == $main::Temperature[0] && $biasVoltage == $BiasList[0]);
|
|
print OF ".alter";
|
|
if ($biasVoltage == $BiasList[0]) {
|
|
print OF ".temp $temperature";
|
|
}
|
|
print OF ".param vbias=$biasVoltage";
|
|
}
|
|
}
|
|
print OF ".end";
|
|
close(OF);
|
|
|
|
#
|
|
# Run simulations and get the results
|
|
#
|
|
|
|
if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null|")) {
|
|
die("ERROR: cannot run $main::simulatorName, stopped");
|
|
}
|
|
$inData=0;$inResults=0;@V=();
|
|
foreach $pin (@main::Outputs) {@{$DC{$pin}}=()}
|
|
while (<SIMULATE>) {
|
|
chomp;
|
|
if (/dc\s+transfer\s+curves/i) {$inResults=1;$inData=0;next}
|
|
if (/job\s+concluded/) {$inResults=0}
|
|
next if (!$inResults);
|
|
s/^\s+//;s/\s+$//;
|
|
if (/^volt\s+(current|voltage)/) {
|
|
chomp($_=<SIMULATE>);s/^\s*(v_)?//;s/\s+$//;$pin=$_;$inData=1;next;
|
|
}
|
|
@Field=split;
|
|
if ($#Field != 1
|
|
|| &modelQa::unScale($Field[0]) !~ /^($main::number)$/
|
|
|| &modelQa::unScale($Field[1]) !~ /^($main::number)$/) {
|
|
$inData=0;next;
|
|
}
|
|
if ($pin eq $main::Outputs[0]) {
|
|
push(@V,&modelQa::unScale($Field[0]));
|
|
}
|
|
push(@{$DC{$pin}},&modelQa::unScale($Field[1]));
|
|
}
|
|
close(SIMULATE);
|
|
|
|
#
|
|
# Write the results to a file
|
|
#
|
|
|
|
if (!open(OF,">$outputFile")) {
|
|
die("ERROR: cannot open file $outputFile, stopped");
|
|
}
|
|
printf OF ("V($main::biasSweepPin)");
|
|
foreach $pin (@main::Outputs) {
|
|
if ($main::isFloatingPin{$pin}) {
|
|
printf OF (" V($pin)");
|
|
} else {
|
|
printf OF (" I($pin)");
|
|
}
|
|
}
|
|
printf OF ("\n");
|
|
for ($i=0;$i<=$#V;++$i) {
|
|
next if (abs($V[$i]-$start) < abs(0.1*$step)); # this is dummy first bias point
|
|
printf OF ("$V[$i]");
|
|
foreach $pin (@main::Outputs) {
|
|
printf OF (" ${$DC{$pin}}[$i]")
|
|
}
|
|
printf OF ("\n");
|
|
}
|
|
close(OF);
|
|
|
|
#
|
|
# Clean up, unless the debug flag was specified
|
|
#
|
|
|
|
if (! $main::debug) {
|
|
unlink($simulate::netlistFile);
|
|
unlink("$simulate::netlistFile.st0");
|
|
if (defined($main::verilogaFile)) {
|
|
unlink("$simulate::netlistFile.val");
|
|
}
|
|
if (!opendir(DIRQA,".")) {
|
|
die("ERROR: cannot open directory ., stopped");
|
|
}
|
|
foreach (grep(/^$simulate::netlistFile\.ic/,readdir(DIRQA))) {unlink($_)}
|
|
closedir(DIRQA);
|
|
unlink("hspice.errors");
|
|
unlink("simout.tmp");
|
|
}
|
|
}
|
|
|
|
sub generateCommonNetlistInfo {
|
|
my($variant,$temperature) = @_;
|
|
my(@Pin_x,$arg,$name,$value,$eFactor,$fFactor,$pin);
|
|
print OF ".option tnom=27 reltol=1u vntol=1n abstol=1f"; # default for HSPICE is 25
|
|
print OF ".temp $temperature";
|
|
if ($variant=~/^scale$/) {
|
|
print OF ".option scale=$main::scaleFactor";
|
|
}
|
|
if ($variant=~/^shrink$/) {
|
|
print OF ".option scale=".(1.0-$main::shrinkPercent*0.01);
|
|
}
|
|
if ($variant=~/_P/) {
|
|
$eFactor=-1;$fFactor=1;
|
|
} else {
|
|
$eFactor=1;$fFactor=-1;
|
|
}
|
|
if ($variant=~/^m$/) {
|
|
if ($main::outputNoise) {
|
|
$fFactor/=sqrt($main::mFactor);
|
|
} else {
|
|
$fFactor/=$main::mFactor;
|
|
}
|
|
}
|
|
if (defined($main::verilogaFile)) {
|
|
print OF ".hdl \"$main::verilogaFile\"";
|
|
}
|
|
foreach $pin (@main::Pin) {push(@Pin_x,"${pin}_x")}
|
|
print OF ".subckt mysub ".join(" ",@Pin_x);
|
|
foreach $pin (@main::Pin) {
|
|
if ($main::isFloatingPin{$pin}) {
|
|
if ($main::outputNoise && $pin eq $main::Outputs[0]) {
|
|
if ($variant =~ /^m$/) {
|
|
$eFactor = sqrt($main::mFactor);
|
|
} else {
|
|
$eFactor = 1;
|
|
}
|
|
print OF "e_$pin ${pin}_x 0 ${pin} 0 $eFactor";
|
|
} else { # assumed "dt" thermal pin, no scaling sign change
|
|
print OF "v_$pin ${pin} ${pin}_x 0";
|
|
}
|
|
} elsif ($variant=~/^Flip/ && defined($main::flipPin{$pin})) {
|
|
print OF "e_$pin ${pin}_v 0 $main::flipPin{$pin}_x 0 $eFactor";
|
|
print OF "v_$pin ${pin}_v ${pin} 0";
|
|
print OF "f_$pin $main::flipPin{$pin}_x 0 v_$pin $fFactor";
|
|
} else {
|
|
print OF "e_$pin ${pin}_v 0 ${pin}_x 0 $eFactor";
|
|
print OF "v_$pin ${pin}_v ${pin} 0";
|
|
print OF "f_$pin ${pin}_x 0 v_$pin $fFactor";
|
|
}
|
|
}
|
|
if (defined($main::verilogaFile)) {
|
|
if ($variant=~/_P/) {
|
|
print OF "${main::keyLetter}1 ".join(" ",@main::Pin)." $main::pTypeSelectionArguments";
|
|
} else {
|
|
print OF "${main::keyLetter}1 ".join(" ",@main::Pin)." $main::nTypeSelectionArguments";
|
|
}
|
|
if ($variant=~/^scale$/) {
|
|
print OF "+ scale=$main::scaleFactor";
|
|
}
|
|
if ($variant=~/^shrink$/) {
|
|
print OF "+ shrink=$main::shrinkPercent";
|
|
}
|
|
} else {
|
|
print OF "${main::keyLetter}1 ".join(" ",@main::Pin)." mymodel";
|
|
}
|
|
foreach $arg (@main::InstanceParameters) {
|
|
($name,$value)=split(/=/,$arg);
|
|
if ($variant=~/^scale$/) {
|
|
if ($main::isLinearScale{$name}) {
|
|
$value/=$main::scaleFactor;
|
|
} elsif ($main::isAreaScale{$name}) {
|
|
$value/=$main::scaleFactor**2;
|
|
}
|
|
}
|
|
if ($variant=~/^shrink$/) {
|
|
if ($main::isLinearScale{$name}) {
|
|
$value/=(1.0-$main::shrinkPercent*0.01);
|
|
} elsif ($main::isAreaScale{$name}) {
|
|
$value/=(1.0-$main::shrinkPercent*0.01)**2;
|
|
}
|
|
}
|
|
print OF "+ $name=$value";
|
|
}
|
|
if ($variant eq "m") {
|
|
print OF "+ m=$main::mFactor";
|
|
}
|
|
if (!defined($main::verilogaFile)) {
|
|
if ($variant=~/_P/) {
|
|
print OF ".model mymodel $main::pTypeSelectionArguments";
|
|
} else {
|
|
print OF ".model mymodel $main::nTypeSelectionArguments";
|
|
}
|
|
}
|
|
foreach $arg (@main::ModelParameters) {
|
|
print OF "+ $arg";
|
|
}
|
|
print OF ".ends";
|
|
}
|
|
|
|
1;
|