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d_lut
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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d_source
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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delay
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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delta-sigma
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add y-axis label
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2022-02-01 12:21:08 +01:00 |
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filesource
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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original-examples
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New names for the (experimental) ramp-time capacitor and inductor code models
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2021-10-29 16:28:57 +02:00 |
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pll
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make simulation faster, allow batch mode
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2020-03-15 08:50:57 +01:00 |
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state
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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table
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New tables for MOS devices
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2022-07-24 15:55:46 +02:00 |
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analog_models1_transient.sp
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xspice examples
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2010-05-14 20:33:20 +00:00 |
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fstest.sp
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'filesource' test
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2011-06-23 19:56:46 +00:00 |
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pwlts1.cir
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example for pwlts source code model
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2022-09-09 15:26:45 +02:00 |
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simple-diode.cir
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Fix a bug in simple diode, when ilimit is set, but not epsilon.
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2022-09-29 16:14:25 +02:00 |
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sine.m
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'filesource' test
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2011-06-23 19:56:46 +00:00 |
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vswitch-test-lin.cir
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Handle the case when control voltages on and off are equal.
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2022-08-05 17:30:08 +02:00 |
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vswitch-test-log.cir
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Handle the case when control voltages on and off are equal.
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2022-08-05 17:30:08 +02:00 |
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xspice_c1.cir
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example input file as cited in manual
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2012-10-21 11:50:23 +02:00 |
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xspice_c2.cir
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whitespace cleanup, add missing trailing newlines
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2010-09-07 19:04:20 +00:00 |
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xspice_c3.cir
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whitespace cleanup, add missing trailing newlines
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2010-09-07 19:04:20 +00:00 |
dc8c7db718