50 lines
1.6 KiB
SourcePawn
50 lines
1.6 KiB
SourcePawn
***** Single NMOS Transistor .measure (Id-Vd) ***
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* Altering device witdth leads to select new model due to binning limits.
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* New model has artificially thick gate oxide (changed from default 3n to 4n)
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* to demonstrate the effect.
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m1 d g s b nch L=0.6u W=9.99u ; W is slightly below binning limit
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vgs g 0 3.5
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vds d 0 3.5
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vs s 0 dc 0
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vb b 0 dc 0
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* model binning
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* uses default parameters, except toxe
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.model nch.1 nmos ( version=4.7 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u toxe=3n )
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.model nch.2 nmos ( version=4.7 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u toxe=4n)
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.control
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dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5
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meas dc is_at FIND i(vs) AT=1
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meas dc is_max max i(vs)
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meas dc vds_at2 when i(vs)=10m
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* starting with branches in descending order of vgs
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* trig ist the first branch which crosses 5mA
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* Targ is the first branch crossing 10mA
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meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1
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* trig ist the first branch which crosses 5mA
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* Targ is the second branch crossing 10mA
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meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2
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alter @m1[w]=10.01u ; W is slightly above binning limit
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dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5
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meas dc is_at FIND i(vs) AT=1
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meas dc is_max max i(vs)
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meas dc vds_at2 when i(vs)=10m
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meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1
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* there is only one branch crossing 10mA, so this second meas fails with targ out of interval
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echo
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echo The next one will fail (no two branches crossing 10 mA):
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meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2
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*rusage all
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plot dc1.i(vs) i(vs)
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.endc
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.end
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