68 lines
2.3 KiB
Plaintext
68 lines
2.3 KiB
Plaintext
* VCO: 7 stage Ring-Osc. made of gain cells BSIM3
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* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495
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* 150 MHz to 900 MHz with control voltage 2.5 to 0.5 V at 3.3 V supply
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* BSIM 3 model data for transistors in main file pll-xspice.cir
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***** ring oscillator as voltage controlled oscillator ***************
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* name: ro_vco
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* aout analog out
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* dout digital out
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* cont control voltage
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* dd supply voltage
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.subckt ro_vco aout dout cont dd
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* ignition circuit (not needed)
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* feedback between in and out, pulse to help start oscillation
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vin inm1 outp7 dc 0
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*vin inm1 outp7 dc 2.5 pulse 2.5 0 0.1n 5n 1 1 1
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*vin2 inp1 outp7 dc -0.5 pulse -0.5 0 0.1n 5n 1 1 1
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vin2 inp1 outm7 dc 0
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vss ss 0 dc 0
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ve sub 0 dc 0
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vpe well 0 dc 3.3
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* gain cell
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.subckt gaincell dd ss sub well co in- in+ out- out+
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mn1 out- in+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u
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mn2 out- out+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u
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mn3 out+ out- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u
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mn4 out+ in- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u
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mp1 out- co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u
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mp2 out+ co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u
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.ends gaincell
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* inverter
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.subckt inv2 dd ss sub well in out
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mn1 out in ss sub n1 w=6u l=0.35u AS=12p AD=12p PS=16u PD=16u
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mp1 out in dd well p1 w=12u l=0.35u AS=24p AD=24p PS=28u PD=28u
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.ends inv2
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* inverter
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.subckt inv1 dd ss sub well in out
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mn1 out in ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u
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mp1 out in dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u
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.ends inv1
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* chain of 25 inverters + output buffer
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xinv1 dd ss sub well cont inm1 inp1 outm1 outp1 gaincell
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xinv2 dd ss sub well cont outp1 outm1 outm2 outp2 gaincell
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xinv3 dd ss sub well cont outp2 outm2 outm3 outp3 gaincell
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xinv4 dd ss sub well cont outp3 outm3 outm4 outp4 gaincell
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xinv5 dd ss sub well cont outp4 outm4 outm5 outp5 gaincell
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xinv6 dd ss sub well cont outp5 outm5 outm6 outp6 gaincell
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xinv7 dd ss sub well cont outp6 outm6 outm7 outp7 gaincell
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* analog out (two stage buffer)
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xinv11 dd 0 sub well outm1 outm2 inv1
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xinv12 dd 0 sub well outm2 aout inv2
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cout aout 0 0.2pF
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*digital out
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abridge1 [aout] [dout] adc_buff
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.model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
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.ends ro_vco
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******************************************************************
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