61 lines
1.6 KiB
Plaintext
61 lines
1.6 KiB
Plaintext
* This file is not intended to be used directly, but by 555.cir.
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* That allows it to be shared by different implemnetations.
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* This sub-circuit simulates the NE555 timer IC, with the very simple
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* digital part as a Verilog module.
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.subckt NE555 trigger threshold reset control output discharge vcc ground
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* Resistor chain
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r1 vcc control 5k
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r2 control trigger_ref 5k
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r3 trigger_ref ground 5k
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* Two XSPICE ADC instances serve as comparators.
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.model comparator adc_bridge(in_low = -0.0001 in_high = 0.0001)
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athresh_comparator [%vd threshold control] [over_threshold] comparator
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atrigger_comparator [%vd trigger_ref trigger] [under_trigger] comparator
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* A tiny Verilog module supplies the flip-flop.
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* The model is supplied by the outer circuit file.
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averilog [ under_trigger over_threshold reset ] [ output qbar ] vlog_ff
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* The discharge transistor and its base resistor.
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rbase qbar discharge_base 10k
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qdischarge discharge discharge_base ground npn_transistor
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.model npn_transistor npn
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.ends ; Ends subcircuit NE555
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* The usual 555 oscillator with threshold connected to discharge.
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.param vcc=12
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X555 trigger_threshold trigger_threshold reset control output discharge vcc 0 ne555
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r1 vcc discharge 10k
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r2 discharge trigger_threshold 10k
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Ct trigger_threshold 0 1uF ic=0
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* A resistive load forces analog output.
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rload output 0 1k
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* A voltage source for power.
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Vcc vcc 0 {vcc}
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* Pulse the Reset signal low for 2uS each 51mS
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Vpulse reset 0 PULSE {vcc} 0.2 0 1u 1u 2u 51m
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.control
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tran 10u 200m uic
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plot trigger_threshold output x555.under_trigger-3 x555.over_threshold-1.5
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.endc
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