47 lines
1.3 KiB
Plaintext
47 lines
1.3 KiB
Plaintext
* state machine example
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* by Marcel Hendrix, Jan. 10th, 2014
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* Define a simple up/down counter that counts clk edges.
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* Digital outputs are on msb+lsb.
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* inputs clock reset outputs (all digital)
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a0 [n_one] clk n_zero [msb lsb] state1
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*.model state1 d_state(state_file = "D:\Software\Spice\various\xspice\state.in")
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.model state1 d_state(state_file = "state.in")
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* Digital "one" and "zero"
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a1 n_one pullup1
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.model pullup1 d_pullup(load = 1pF)
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a2 n_zero pulldown1
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.model pulldown1 d_pulldown(load = 1pF)
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* Convert the digital outputs to analog so we can conveniently plot them
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a3 [msb] [out_msb] dac1
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a4 [lsb] [out_lsb] dac1
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.model dac1 dac_bridge(out_low = 0 out_high = 5 out_undef = 2.5)
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* The digital VCO needs an analog control voltage
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Vcnt cntl 0 pulse(-1V 1V 0 5ms 4ms 1ms 1)
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* Digital VCO to drive state-machine (counter)
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a5 cntl clk var_clock
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.model var_clock d_osc(cntl_array = [-2 -1 1 2] freq_array = [1e3 1e3 10e3 10e3]
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+ duty_cycle = 0.1)
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.control
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tran 1us 10ms
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rusage
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write spifsim.raw
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plot cntl out_msb+2 out_lsb+8
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eprvcd n_one clk n_zero msb lsb > spifsim.vcd
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* plotting the vcd file (e.g. with GTKWave)
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if $oscompiled = 1 | $oscompiled = 8 ; MS Windows
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* For Windows: returns control to ngspice
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shell start gtkwave spifsim.vcd --script $inputdir/nggtk.tcl
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else
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* Others
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shell gtkwave spifsim.vcd --script nggtk.tcl &
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end
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.endc
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.end
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