34 lines
597 B
Plaintext
34 lines
597 B
Plaintext
Mixed IO sizes
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*
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* This circuit contains a collection of digital and analog
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* models with saclar and vector inputs of varying sizes.
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*
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.tran 1e-5 1e-3
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*
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v1 1 0 0.0 pulse(0 1 1e-4)
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r1 1 0 1k
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*
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v2 2 0 0.0 sin(0 1 2k)
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r2 2 0 1k
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*
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abridge1 [1] [enable] atod
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.model atod adc_bridge
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*
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aosc [enable clk] clk nand
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.model nand d_nand (rise_delay=1e-4 fall_delay=1e-4)
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*
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ainv clk clk_bar inv
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.model inv d_inverter (rise_delay=1e-5 fall_delay=1e-5)
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*
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adac [clk clk_bar] [3 4] dac
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.model dac dac_bridge (t_rise=1e-5 t_fall=1e-5)
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*
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asum [1 2 3 4] 5 sum
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.model sum summer
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*
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r3 3 0 1k
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r4 4 0 1k
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r5 5 0 1k
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*
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.end
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