dwarning 33fb5f20d9 vbic: rm obsolete regression test

2024-04-24 10:35:44 +02:00

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adms

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cider

When Cider models are present, a normal batch mode sp_shutdown (for example, ngspice -b cmosinv.cir) will call com_quit(NULL). This cleans up so that valgrind will find no leaks in Cider devices after sp_shutdown. To disable this feature, set the environment variable CIDER_COM_QUIT="OFF". Even though it really does not matter that Cider memory is cleared just before exit, it makes it cleaner for valgrind checks.

2023-07-15 11:32:37 +02:00

control_structs

S-parameters: Replace S11 by S_1_1 etc. to avoid ambiguity

2022-04-29 07:29:14 +02:00

ddt

Remove unused variable debarr.

2022-12-11 15:39:10 +01:00

digital

Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE.

2023-07-31 14:27:59 +02:00

hicum2

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inductive-systems

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klu/Circuits

Added missing ISCAS85 libraries

2023-08-16 11:14:18 +02:00

loops

Repeat loop requires plain number, transformed vector, or transformed variable

2024-03-19 17:05:10 +01:00

measure

measure example with expression evaluation

2024-03-29 17:12:40 +01:00

memristor

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Monte_Carlo

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mos

MOS example files updated and moved to its own directory

2023-01-24 15:17:31 +01:00

noise

implement osdi noise support

2023-11-04 19:36:30 +01:00

numparam

Add a simple example of using string-valued parameters.

2023-01-09 16:33:53 +01:00

optran

special ngbehavior needed

2023-01-09 16:31:01 +01:00

osdi

add examples for OSDI noise

2023-11-04 19:36:30 +01:00

p-to-n-examples

Use sparse, as KLU will fail.

2023-09-10 13:43:09 +02:00

paranoia

Fix some typos.

2023-12-18 20:13:06 +01:00

plot

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probe

Enable power measurement for W switch

2022-10-07 13:18:51 +02:00

proc2mod

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pss

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snapshot

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soa

Add a comment to say that LT/PSPICE compatability is needed.

2023-07-31 14:29:50 +02:00

soi

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sp

better visibility

2023-07-31 14:30:37 +02:00

svg

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tclspice

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transient-noise

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TransImpedanceAmp

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TransmissionLines

Better visibility of the results

2023-07-15 11:11:48 +02:00

utf-8/стекло

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various

Add a transformer with parameters on the .subckt line

2024-01-24 10:11:44 +01:00

vbic

vbic: rm obsolete regression test

2024-04-24 10:35:44 +02:00

vdmos

Add vto model parameter (the default has changed!), add .ic

2023-05-27 10:47:43 +02:00

xspice

Add the support files for co-simulation with Verilog code

2023-11-27 20:55:59 +00:00