dwarning bd5379d760 one tran analysis is sufficient

2018-09-14 20:34:27 +02:00

..

d_lut

examples/xspice/d_lut/mult4bit.spi, example for d_lut and d_genlut

2017-05-01 22:11:50 +02:00

d_source

add plotting to the example

2018-08-27 12:20:30 +02:00

delta-sigma

example for .options interp (reduces memory, speeds up plotting)

2014-02-01 14:31:38 +01:00

filesource

xspice filesource example

2018-07-28 11:45:33 +02:00

original-examples

Original examples fixed and moved to here

2018-07-28 13:45:41 +02:00

pll

add BSIM3 model parameters for loop filer with transistor charge pump

2012-08-05 20:15:53 +02:00

state

add plotting with internal analog plot

2018-08-10 19:55:52 +02:00

table

one tran analysis is sufficient

2018-09-14 20:34:27 +02:00

analog_models1_transient.sp

xspice examples

2010-05-14 20:33:20 +00:00

fstest.sp

'filesource' test

2011-06-23 19:56:46 +00:00

sine.m

'filesource' test

2011-06-23 19:56:46 +00:00

xspice_c1.cir

example input file as cited in manual

2012-10-21 11:50:23 +02:00

xspice_c2.cir

whitespace cleanup, add missing trailing newlines

2010-09-07 19:04:20 +00:00

xspice_c3.cir

whitespace cleanup, add missing trailing newlines

2010-09-07 19:04:20 +00:00