24 lines
446 B
Plaintext
24 lines
446 B
Plaintext
state test
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* transient simulation only
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* 0 <= astate_no <= 3
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* out delayed by astate_no accepted time steps
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* current or voltage in- and outputs
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Vsin1 in 0 SIN (0 1.5 1k)
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Rin in 0 1.5
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astate1 in out newstate
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.model newstate astate(astate_no=2)
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astate2 %vnam(Vsin1) %id(out2+ 0) newstate2
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.model newstate2 astate(astate_no=3)
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R2 out2+ 0 0.9
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.control
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tran 10u 2m
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set xbrushwidth=2
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plot v(in) v(out) v(out2+)
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.endc
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.end
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