142 lines
4.7 KiB
Plaintext
142 lines
4.7 KiB
Plaintext
// ****************************************************************************
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// * BSIM-CMG 111.0.0 released by Harshit Agarwal on 09/12/2019 *
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// * BSIM Common Multi-Gate Model (Verilog-A) *
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// ****************************************************************************
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// ****************************************************************************
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// * Copyright © 2019 University of California *
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// * *
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// * Project director: Prof. Chenming Hu *
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// * *
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// * Current developers: Harshit Agarwal (Postdoc) *
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// * Pragya Kushwaha (Postdoc) *
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// * Avirup Dasgupta (Postdoc) *
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// * Yen-Kai Lin (Ph.D. student) *
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// * Ming-Yen Kao (Ph.D. student) *
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// ****************************************************************************
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/*
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Licensed under Educational Community License, Version 2.0 (the "License"); you may
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not use this file except in compliance with the License. You may obtain a copy of the license at
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http://opensource.org/licenses/ECL-2.0
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Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations
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under the License.
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BSIM-CMG model is supported by the members of Silicon Integration Initiative's Compact Model Coalition. A link to the most recent version of this
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standard can be found at: http://www.si2.org/cmc
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*/
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// Source/drain resistances
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Dr = 0.0; Rdrain = 0.0; Rsource = 0.0; Rdsi = 0.0;
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// Temperature effects
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CJS_t = 0.0; CJSWS_t = 0.0; CJSWGD_t = 0.0;
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CJD_t = 0.0; CJSWD_t = 0.0; CJSWGS_t = 0.0;
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PBS_t = 0.0; PBSWS_t = 0.0; PBSWGS_t = 0.0;
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PBD_t = 0.0; PBSWD_t = 0.0; PBSWGD_t = 0.0;
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JSS_t = 0.0; JSWS_t = 0.0; JSWGS_t = 0.0;
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JSD_t = 0.0; JSWD_t = 0.0; JSWGD_t = 0.0;
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JTSS_t = 0.0; JTSD_t = 0.0;
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JTSSWS_t = 0.0; JTSSWD_t = 0.0;
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JTSSWGS_t = 0.0; JTSSWGD_t = 0.0;
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NJTS_t = 0.0; NJTSD_t = 0.0;
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NJTSSW_t = 0.0; NJTSSWD_t = 0.0;
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NJTSSWG_t = 0.0; NJTSSWGD_t = 0.0;
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RSDRR_t = 0.0; RDDRR_t = 0.0;
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UAR_t = 0.0; UC_t = 0.0; UCR_t = 0.0; UDR_t = 0.0;
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VSATR_t = 0.0; VSAT1R_t = 0.0; MEXPR_t = 0.0; PTWGR_t = 0.0;
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// Quantum mechanical correction
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Tcen0 = 0.0;
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// Midpoint potential and charge
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qba = 0.0; u0r = 0.0;
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// Geometry-dependent fringe capacitance
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Cfr_geo = 0.0;
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// Gate resistance
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ggeltd = 0.0;
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// Gate current
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igbinv = 0.0; igbacc = 0.0;
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igbs = 0.0; igbd = 0.0;
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igcs = 0.0; igcd = 0.0;
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igs = 0.0; igd = 0.0;
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// GIDL/GISL
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igisl = 0.0; igidl = 0.0;
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// Impact ionization current
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Iii = 0.0;
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// Accumulation capacitance
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cox_acc = 0.0; qg_acc = 0.0; qb_acc = 0.0;
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// Parasitic capacitance
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qgs_ov = 0.0; qgd_ov = 0.0;
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// Junction current and capacitance
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Ies = 0.0; Ied = 0.0;
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Czbs = 0.0; Czbssw = 0.0; Czbsswg = 0.0;
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Czbd = 0.0; Czbdsw = 0.0; Czbdswg = 0.0;
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Qesj = 0.0; Qedj = 0.0;
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Isbs = 0.0; Isbd = 0.0;
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Nvtms = 0.0; Nvtmd = 0.0;
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SslpFwd = 0.0; IVjsmFwd = 0.0; VjsmFwd = 0.0; XExpBVS = 0.0;
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SslpRev = 0.0; IVjsmRev = 0.0; VjsmRev = 0.0;
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DslpFwd = 0.0; IVjdmFwd = 0.0; VjdmFwd = 0.0; XExpBVD = 0.0;
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DslpRev = 0.0; IVjdmRev = 0.0; VjdmRev = 0.0;
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vec1s = 0.0; pb21s = 0.0;
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vec2s = 0.0; pb22s = 0.0;
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vec3s = 0.0; pb23s = 0.0;
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vec1d = 0.0; pb21d = 0.0;
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vec2d = 0.0; pb22d = 0.0;
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vec3d = 0.0; pb23d = 0.0;
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// NQS gate resistance
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gcrg = 0.0; gtau = 0.0;
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// Thermal noise
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sid = 0.0;
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// Correlated thermal noise
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Dr0 = 0.0; ctnoi = 0.0; sigrat = 0.0;
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// Self-heating
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gth = 0.0; cth = 0.0;
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// Short channel effects
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CITR_i = 0.0; CDSCDR_i = 0.0; ETA0R_i = 0.0; DVTSHIFTR_i = 0.0;
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// Body effect
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veseff = 0.0;
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PHIBE_i = 0.0; K1_i = 0.0; K11_i = 0.0; K2SAT_i = 0.0; K2SAT1_i = 0.0;
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K2_i = 0.0; K21_i = 0.0;
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// Velocity satuation
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VSATR_i = 0.0; VSAT1R_i = 0.0; KSATIVR_i = 0.0; MEXPR_i = 0.0;
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PTWGR_i = 0.0; ATR_i = 0.0;
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// Mobility
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U0R_i = 0.0; UPR_i = 0.0; UAR_i = 0.0; UC_i = 0.0; UCR_i = 0.0; EUR_i = 0.0;
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UDR_i = 0.0; UTER_i = 0.0; UTLR_i = 0.0;
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UA1R_i = 0.0; UC1_i = 0.0; UC1R_i = 0.0; UD1R_i = 0.0;
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// DIBL
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PDIBL1R_i = 0.0; PDIBL2R_i = 0.0;
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// Channel length modulation
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PCLMR_i = 0.0;
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// Overlap capacitance
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CGSO_i = 0.0; CGDO_i = 0.0;
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// NQS gate resistance model & charge deficit model
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XRCRG1_i = 0.0; XRCRG2_i = 0.0;
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// Unified FinFET compact model
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Cins = 0.0; Ach = 0.0; Weff_UFCM = 0.0; rc = 0.0; Qdep_ov_Cins = 0.0;
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qi_acc_for_QM = 0.0; nq = 0.0;
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