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ngspice/test_cases
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Holger Vogt a9cb0fd26e New and updated test cases 2022-12-27 14:00:28 +01:00
..
ECL New and updated test cases 2022-12-27 14:00:28 +01:00
capacitor prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
cccs prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
ccvs prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
diode prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
diode_mod New and updated test cases 2022-12-27 14:00:28 +01:00
hicuml0 New and updated test cases 2022-12-27 14:00:28 +01:00
hicuml2 prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
inductor prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
multiple_devices prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
node_collapsing prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
resistor prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
test-bsimbulk New and updated test cases 2022-12-27 14:00:28 +01:00
test-bsimcmg/Modelcards New and updated test cases 2022-12-27 14:00:28 +01:00
test-psp103 New and updated test cases 2022-12-27 14:00:28 +01:00
vccs prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
vcvs prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00
testing.py prototype for Verilog-A integration using OSDI and OpenVAF 2022-12-27 13:51:57 +01:00