137 lines
3.3 KiB
Plaintext
137 lines
3.3 KiB
Plaintext
Mixed IO types with conversion of Pspice nand and divider.
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* This circuit contains a mixture of IO types, including
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* analog, digital, user-defined (real), and 'null'.
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*
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* The circuit demonstrates the use of the digital and
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* user-defined node capability to model system-level designs
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* such as sampled-data filters. The simulated circuit
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* contains a digital oscillator enabled after 100us. The
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* square wave oscillator output is divided by 8 with a
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* ripple counter. The result is passed through a digital
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* filter to convert it to a sine wave.
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*
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.tran 1e-5 1e-3
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.save all
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*
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v1 1 0 0.0 pulse(0 1 1e-4 1e-6)
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r1 1 0 1k
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*
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abridge1 [1] [enable] atod
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.model atod adc_bridge
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*
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.SUBCKT NAND2 D0A D0B Q0BAR
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+ OPTIONAL: DPWR=$G_DPWR DGND=$D_DGND
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+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
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U1 NAND(2) DPWR DGND
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+ D0A D0B Q0BAR
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+ DLY_XYZ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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.MODEL DLY_XYZ UGATE (TPLHMN=8US TPLHTY=10US TPLHMX=15US
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+ TPHLMN=8US TPHLTY=10US TPHLMX=15US)
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.ENDS NAND2
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*
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x2000 enable clk clk nand2
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*
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*** subckt nand2 replaces these
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*** aclk [enable clk] clk nand
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*** .model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
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*
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.subckt DIVIDER8 clock DIV8_O DIV4_O DIV2_O
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+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
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+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
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U1 DFF(1) DPWR DGND
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+ $D_HI $D_HI clock DIV2_O $D_NC DIV2_O
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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U2 DFF(1) DPWR DGND
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+ $D_HI $D_HI DIV2_O DIV4_O $D_NC DIV4_O
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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U3 DFF(1) DPWR DGND
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+ $D_HI $D_HI DIV4_O DIV8_O $D_NC DIV8_O
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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.MODEL D0_EFF UEFF ()
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.ENDS DIVIDER8
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*
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x1000 clk div8_out div4_out div2_out divider8
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*
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*** subckt divider8 replaces these
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*** adiv2 div2_out clk NULL NULL NULL div2_out dff
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*** adiv4 div4_out div2_out NULL NULL NULL div4_out dff
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*** adiv8 div8_out div4_out NULL NULL NULL div8_out dff
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*** .model dff d_dff
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*
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abridge2 div8_out enable filt_in node_bridge2
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.model node_bridge2 d_to_real (zero=-1 one=1)
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*
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xfilter filt_in clk filt_out dig_filter
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*
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abridge3 filt_out a_out node_bridge3
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.model node_bridge3 real_to_v
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*
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rlpf1 a_out oa_minus 10k
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*
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xlpf 0 oa_minus lpf_out opamp
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*
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rlpf2 oa_minus lpf_out 10k
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clpf lpf_out oa_minus 0.01uF
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*
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*
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.subckt dig_filter filt_in clk filt_out
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*
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.model n0 real_gain (gain=1.0)
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.model n1 real_gain (gain=2.0)
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.model n2 real_gain (gain=1.0)
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.model g1 real_gain (gain=0.125)
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.model zm1 real_delay
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.model d0a real_gain (gain=-0.75)
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.model d1a real_gain (gain=0.5625)
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.model d0b real_gain (gain=-0.3438)
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.model d1b real_gain (gain=1.0)
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*
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an0a filt_in x0a n0
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an1a filt_in x1a n1
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an2a filt_in x2a n2
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*
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az0a x0a clk x1a zm1
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az1a x1a clk x2a zm1
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*
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ad0a x2a x0a d0a
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ad1a x2a x1a d1a
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*
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az2a x2a filt1_out g1
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az3a filt1_out clk filt2_in zm1
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*
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an0b filt2_in x0b n0
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an1b filt2_in x1b n1
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an2b filt2_in x2b n2
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*
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az0b x0b clk x1b zm1
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az1b x1b clk x2b zm1
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*
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ad0 x2b x0b d0b
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ad1 x2b x1b d1b
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*
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az2b x2b clk filt_out zm1
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*
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.ends dig_filter
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*
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*
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.subckt opamp plus minus out
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*
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r1 plus minus 300k
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a1 %vd (plus minus) outint lim
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.model lim limit (out_lower_limit = -12 out_upper_limit = 12
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+ fraction = true limit_range = 0.2 gain=300e3)
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r3 outint out 50.0
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r2 out 0 1e12
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*
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.ends opamp
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*
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.control
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run
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plot lpf_out v(a_out)
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plot v(xlpf.outint)
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*eprint xfilter.x1a
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eprint div8_out
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.endc
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*
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.end
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