ngspice/examples
Holger Vogt 507351ae01 A digital NAND gate 9-stage ring oscillator (less than 30ms simulation time) 2026-06-06 14:26:25 +02:00
..
Monte_Carlo
SkywaterOpenSourcePDK Add two simple Skywater PDK examples, inverter and ISCAS85 C7552 2025-05-24 11:13:43 +02:00
TransImpedanceAmp
TransmissionLines
cider Enable CIDER with KLU for DC, OP, and TRAN analyses. Small signal AC analysis is not yet supported for CIDER complex valued device KLU matrices. The examples/cider testcases produce printed simulation result values which have slight differences between Sparse and KLU. Differences are probably expected and in a few cases are ~1-2%, sometimes a little more. This should be good enough for most CIDER analyses. Francesco did a good piece of work. Runtimes are significantly shorter with KLU. 2026-02-03 13:55:12 +01:00
control_structs
ddt
digital Corrections to voltage pulses. 2026-04-04 13:37:32 +02:00
hicum2
inductive-systems
klu/Circuits
loops
measure Enable expressions in a meas statement within a .control section, like 2025-07-29 10:37:59 +02:00
memristor Better graphics 2026-02-03 14:23:07 +01:00
mos Update: add frequency measurement and temperature dependency. 2026-02-03 14:14:18 +01:00
noise
numparam
optran F5 example removed, obsolete or needs to be improved. 2026-02-03 14:21:38 +01:00
osdi options are not required 2025-05-24 10:58:45 +02:00
p-to-n-examples
paranoia
plot
probe Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch. 2026-02-03 14:21:50 +01:00
proc2mod
pss Show equal x axes 2026-04-24 20:49:14 +02:00
shared Add an extended shared library test program with additional 2025-05-24 11:28:07 +02:00
snapshot
soa
soi enable simulation with 'option newtrunc' 2026-02-03 14:22:12 +01:00
sp Improve S-parameter example: change node names to make plot clearer, 2026-04-01 07:35:20 +01:00
svg
tclspice
transient-noise Update test description 2026-02-03 14:16:23 +01:00
utf-8/стекло
various Using mtimeavg 2026-02-03 14:23:41 +01:00
vbic
vdmos Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch. 2026-02-03 14:21:50 +01:00
wave Correct paths in example file 2026-05-15 01:00:56 +02:00
xspice A digital NAND gate 9-stage ring oscillator (less than 30ms simulation time) 2026-06-06 14:26:25 +02:00