Holger Vogt afde37c35d add y-axis label		2022-02-01 12:21:08 +01:00
..
d_lut	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
d_source	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delay	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delta-sigma	add y-axis label	2022-02-01 12:21:08 +01:00
filesource	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
original-examples	New names for the (experimental) ramp-time capacitor and inductor code models	2021-10-29 16:28:57 +02:00
pll	make simulation faster, allow batch mode	2020-03-15 08:50:57 +01:00
state	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
table	one tran analysis is sufficient	2018-09-14 20:34:27 +02:00
analog_models1_transient.sp	xspice examples	2010-05-14 20:33:20 +00:00
fstest.sp	'filesource' test	2011-06-23 19:56:46 +00:00
sine.m	'filesource' test	2011-06-23 19:56:46 +00:00
xspice_c1.cir	example input file as cited in manual	2012-10-21 11:50:23 +02:00
xspice_c2.cir	whitespace cleanup, add missing trailing newlines	2010-09-07 19:04:20 +00:00
xspice_c3.cir	whitespace cleanup, add missing trailing newlines	2010-09-07 19:04:20 +00:00