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ECL
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New and updated test cases
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2022-12-16 21:55:18 +01:00 |
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capacitor
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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cccs
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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ccvs
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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diode
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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diode_mod
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New and updated test cases
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2022-12-16 21:55:18 +01:00 |
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hicuml0
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New and updated test cases
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2022-12-16 21:55:18 +01:00 |
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hicuml2
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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inductor
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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multiple_devices
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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node_collapsing
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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resistor
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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test-bsimbulk
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device name now starts with N (instead of A).
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2022-12-16 21:55:19 +01:00 |
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test-bsimcmg/Modelcards
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New and updated test cases
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2022-12-16 21:55:18 +01:00 |
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test-psp102
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(non-working) PSP102 examples
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2022-12-16 21:55:19 +01:00 |
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test-psp103
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Replace 'a' by 'n' for OSDI device
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2022-12-16 21:55:19 +01:00 |
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vccs
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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vcvs
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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testing.py
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prototype for Verilog-A integration using OSDI and OpenVAF
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2022-12-16 21:55:17 +01:00 |
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