60 lines
1.1 KiB
Plaintext
60 lines
1.1 KiB
Plaintext
* 51 stage Ring-Osc. BSIM3, transient noise
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* will need 45 min on a i7 860 with 4 threads
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* closes the loop between inverters xinv1 and xinv5
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vin in out dc 0.5 pulse 0.5 0 0.1n 5n 1 1 1
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vdd dd 0 dc 0 pulse 0 2.2 0 1n 1 1 1
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vss ss 0 dc 0
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ve sub 0 dc 0
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vpe well 0 2.2
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* noisy inverters
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xiinv2 dd ss sub well out25 out50 inv253
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xiinv1 dd ss sub well in out25 inv253
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*very noisy inverter
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xiinv5 dd ss sub well out50 out inv1_2
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*output amplifier
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xiinv11 dd ss sub well out25 bufout inv1
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cout bufout ss 0.2pF
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.option itl1=500 gmin=1e-15 itl4=10 noacct
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* .dc vdd 0 2 0.01
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.tran 0.01n 500n
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.save in bufout v(t1)
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.include modelcard.nmos
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.include modelcard.pmos
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.include noilib-demo.h
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.control
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unset ngdebug
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* first run
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save bufout $ needed for restricting memory usage
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rusage
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tran 8p 10000n
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rusage
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plot bufout xlimit 90n 95n
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linearize
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fft bufout
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* next run
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reset
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save bufout
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alter @v.xiinv5.vn1[trnoise] = [ 0 0 0 0 ] $ no noise
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tran 8p 10000n
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rusage
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plot bufout xlimit 90n 95n
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linearize
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fft bufout
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plot mag(bufout) mag(sp2.bufout) xlimit 0 2G ylimit 1e-11 0.1 ylog
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.endc
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.end
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