69 lines
1.5 KiB
SourcePawn
69 lines
1.5 KiB
SourcePawn
Code Model Test - 3d Table Model
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* Ring oscillator made of inverters
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*
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*** analysis type ***
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.control
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option trtol=1
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*dc V1 0.0 1.7 0.1 V2 0.3 1.7 0.3
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*op
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tran 100p 20n
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*plot i(Vs) i(Vs2)
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plot v(in1)
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rusage
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.endc
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*
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*** input sources ***
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*
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v1 d 0 DC 1.5
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v2 g 0 DC 1.5
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Vs s 0 0
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Vs2 s2 0 0
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vsinv vss 0 0
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vdinv vdd 0 1.5
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*
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*********************
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*xmosnt d g s tbmosn
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*mn2 d g s2 s2 n1 l=0.13u w=10u ad=5p pd=6u as=5p ps=6u rgeoMod=1
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.subckt inv vd vs in out
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*mp2 out in vd vd p1 l=0.13u w=10u ad=5p pd=6u as=5p ps=6u
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xmospt out in vd vd tbmosp
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*mn2 out in vs vs n1 l=0.13u w=5u ad=5p pd=6u as=5p ps=6u
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xmosnt out in vs vs tbmosn
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.ends
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xmosinv1 vdd vss in1 out1 inv
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xmosinv2 vdd vss out1 out2 inv
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xmosinv3 vdd vss out2 out3 inv
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xmosinv4 vdd vss out3 out4 inv
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xmosinv5 vdd vss out4 in1 inv
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.subckt tbmosn d g s b
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*** table model of nmos transistor ***
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cdg d g 0.01p
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csg s g 0.014p
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amos1 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable1
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.model mostable1 table3d (offset=0.0 gain=0.5 order=3 file="bsim4n-3d-1.table")
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* NMOS L=0.13u W=10.0u rgeoMod=1
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* BSIM 4.7
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* change width of transistor by modifying parameter "gain"
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.ends
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.subckt tbmosp d g s b
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*** table model of pmos transistor ***
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cdg d g 0.01p
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csg s g 0.014p
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amos2 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable2
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.model mostable2 table3d (offset=0.0 gain=1 order=3 file="bsim4p-3d-1.table")
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* PMOS L=0.13u W=10.0u rgeoMod=1
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* BSIM 4.7
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* change width of transistor by modifying parameter "gain"
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.ends
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.include ./modelcards/modelcard.nmos
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.include ./modelcards/modelcard.pmos
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.end
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