47 lines
1.3 KiB
Plaintext
47 lines
1.3 KiB
Plaintext
* delta sigma modulator
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* first order, continuous time
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.subckt mod1 ainp ainn dclk ddffq ddffqb
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* integrator and summer
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Ri1 ainn inintn 500
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Rf1 adffq inintn 500
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Cint1 outintp inintn 1n
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.IC v(outintp) = 0 v(inintp) = 0
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*
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Rshunt1 outintp 0 100Meg
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Rshunt2 initn 0 100Meg
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*
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Ri2 ainp inintp 500
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Rf2 adffqb inintp 500
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Cint2 outintn inintp 1n
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.IC v(outintn) = 0 v(inintn) = 0
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*
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Rshunt3 outintn 0 100Meg
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Rshunt4 inintp 0 100Meg
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*
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aint %vd(inintp inintn) %vd(outintp outintn) amp
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.model amp gain ( in_offset =0.0 gain =100000
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+ out_offset = 0)
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* latched comparator (code model or B source, analog in, digital out)
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*acomp %vd(outintp outintn) acompout limit5
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*.model limit5 limit(in_offset=0 gain=100000 out_lower_limit=-1.0
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*+ out_upper_limit=1.0 limit_range=0.10 fraction=FALSE)
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*
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BComp acompout 0 V = (V(outintp) - V(outintn)) >= 0 ? 1 : -1
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*
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abridge2 [acompout] [dcompout] adc_buff
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.model adc_buff adc_bridge(in_low = 0 in_high = 0)
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*
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* D flip flop: data clk set reset out nout
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adff1 dcompout dclk ds drs ddffq ddffqb flop2
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.model flop2 d_dff(clk_delay = 1e-9 set_delay = 1.0e-9
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+ reset_delay = 1.0e-9 ic = 0 rise_delay = 1.0e-9
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+ fall_delay = 1e-9)
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abridge1 [ddffq ddffqb dclk] [adffq adffqb aclk] dac1
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.model dac1 dac_bridge(out_low = -1 out_high = 1 out_undef = 0
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+ input_load = 5.0e-12
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.ends mod1
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