11 lines
461 B
Plaintext
11 lines
461 B
Plaintext
The circuit adc.cir in this directory illustrates the use of the d_cosim
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XSPICE code model as a container for a Verilog simulation. Before the
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simulation can be run, the Verilog code must be compiled by Verilator
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using the command:
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ngspice vlnggen adc.v
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That should create a shared library file, adc.so (or adc.DLL on Windows)
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that will be loaded by the d_cosim code model. The compiled Verilog code that
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it contains will be executed during simulation.
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