86 lines
1.8 KiB
Plaintext
86 lines
1.8 KiB
Plaintext
Conversion of Pspice full adder
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* ----------------------------------------------------------- 74LV86A ------
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* Quad 2-Input Exclusive-Or Gate
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*
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* TI PDF File
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* bss 2/24/03
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*
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.SUBCKT 74LV86A 1A 1B 1Y
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+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
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+ params: MNTYMXDLY=0 IO_LEVEL=0
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U1 xor DPWR_3V DGND_3V
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+ 1A 1B 1Y
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+ DLY_LV86 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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.model DLY_LV86 ugate (tplhTY=7.4ns tplhMX=14.5ns tphlTY=7.4ns tphlMX=14.5ns)
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.ENDS 74LV86A
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* ----------------------------------------------------------- 74LV08A ------
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* Quad 2-Input And Gate
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*
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* TI PDF File
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* bss 2/21/03
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*
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.SUBCKT 74LV08A 1A 1B 1Y
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+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
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+ params: MNTYMXDLY=0 IO_LEVEL=0
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U1 and(2) DPWR_3V DGND_3V
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+ 1A 1B 1Y
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+ DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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.model DLY_LV08 ugate (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns)
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.ENDS 74LV08A
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* ----------------------------------------------------------- 74LV32A ------
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* Quad 2-Input Or Gate
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*
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* TI PDF File
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* bss 2/24/03
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*
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.SUBCKT 74LV32A 1A 1B 1Y
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+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
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+ params: MNTYMXDLY=0 IO_LEVEL=0
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U1 or(2) DPWR_3V DGND_3V
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+ 1A 1B 1Y
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+ DLY_LV32 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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.model DLY_LV32 ugate (
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+ tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns)
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.ENDS 74LV32A
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.subckt hadd a b sum carry
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x1_xor a b sum 74lv86a
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x2_and a b carry 74lv08a
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.ends hadd
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.subckt fadd a b cin sum cout
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x1_ha a b 1 2 hadd
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x2_ha 1 cin sum 3 hadd
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x3_or 3 2 cout 74lv32a
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.ends fadd
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x1 a b cin sum cout fadd
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a2 [a b cin] input_vec1
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.model input_vec1 d_source(input_file = "ex4.stim")
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.tran 0.5ns 1650ns 0
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.save all
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.control
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listing expand
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run
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display
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edisplay
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eprint a b cin sum cout
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set xbrushwidth=3
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plot a b cin cout sum digitop
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*quit
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.endc
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.end
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