80 lines
1.4 KiB
Plaintext
80 lines
1.4 KiB
Plaintext
4 bit adder
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* Models:
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.MODEL dmod D
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.MODEL qmod NPN(level=1 BF=75 RB=100 CJE=1PF CJC=3PF)
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.options noacct
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.SUBCKT NAND 1 2 3 4
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* noeuds: entrees(2) sortie vcc
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q1 9 5 1 qmod
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d1clamp 0 1 dmod
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q2 9 5 2 qmod
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d2clamp 0 2 dmod
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rb 4 5 4k
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r1 4 6 1.6k
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q3 6 9 8 qmod
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r2 8 0 1k
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rc 4 7 130
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q4 7 6 10 qmod
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dvbedrop 10 3 dmod
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q5 3 8 0 qmod
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.ends NAND
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.SUBCKT ONEBIT 1 2 3 4 5 6
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* noeuds entrees(2) ,carryin, sortie, carryout, vcc
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x1 1 2 7 6 NAND
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x2 1 7 8 6 NAND
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x3 2 7 9 6 NAND
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x4 8 9 10 6 NAND
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x5 3 10 11 6 NAND
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x6 3 11 12 6 NAND
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x7 10 11 13 6 NAND
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x8 12 13 4 6 NAND
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x9 11 7 5 6 NAND
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.ends ONEBIT
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.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
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* noeuds
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x1 1 2 7 5 10 9 ONEBIT
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x2 3 4 10 6 8 9 ONEBIT
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.ends TWOBIT
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.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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x1 1 2 3 4 9 10 13 16 15 TWOBIT
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x2 5 6 7 8 11 12 16 14 15 TWOBIT
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.ends FOURBIT
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* Inputs/Supplies:
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vcc 99 0 DC 5V
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VIN1A 1 0 DC 0 pulse(0 3 0 10ns 10ns 10ns 50ns)
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VIN1B 2 0 DC 0 pulse(0 3 0 10ns 10ns 20ns 100ns)
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VIN2A 3 0 DC 0 pulse(0 3 0 10ns 10ns 40ns 200ns)
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VIN2B 4 0 DC 0 pulse(0 3 0 10ns 10ns 80ns 400ns)
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VIN3A 5 0 DC 0 pulse(0 3 0 10ns 10ns 160ns 800ns)
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VIN3B 6 0 DC 0 pulse(0 3 0 10ns 10ns 320ns 1600ns)
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VIN4A 7 0 DC 0 pulse(0 3 0 10ns 10ns 640ns 3200ns)
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VIN4B 8 0 DC 0 pulse(0 3 0 10ns 10ns 1280ns 6400ns)
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* Circuit description:
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x1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
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rbit0 9 0 1k
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rbit1 10 0 1k
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rbit2 11 0 1k
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rbit3 12 0 1k
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rcout 13 0 1k
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* Analysys:
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.tran 1ns 6ns
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.print tran v(1)
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.end
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