50 lines
1.1 KiB
Plaintext
50 lines
1.1 KiB
Plaintext
Conversion of Pspice counter
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.subckt counter high clear clk qa qb qc qd 5 7 9 11
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U1 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR CLK HIGH HIGH QA 5
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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U2 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR QA HIGH HIGH QB 7
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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U3 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR QB HIGH HIGH QC 9
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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U4 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR QC HIGH HIGH QD 11
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+ D0_EFF IO_STD IO_LEVEL=0 MNTYMXDLY=2
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.MODEL D0_EFF UEFF ()
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.ends counter
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*** input sources ***
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vclk 100 0 pulse( 0.0 1.0 50ns 0ns 0ns 50ns 100ns )
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vreset 200 0 pulse( 1.0 0.0 10ns 0ns 0ns 50ns )
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vhigh 300 0 DC 1.0
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*** adc_bridge blocks ***
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aconverter [100 200 300] [clock clr hi] adc_bridge1
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.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9
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+ rise_delay=1.0e-12 fall_delay=1.0e-12)
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*** resistors to ground ***
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r1 100 0 1k
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r2 200 0 1k
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r3 300 0 1k
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r4 q1b 0 1k
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r5 q2b 0 1k
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r6 q3b 0 1k
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r7 q4b 0 1k
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x1 hi clr clock q1 q2 q3 q4 q1b q2b q3b q4b counter
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.TRAN 1e-008 1u 0
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.save all
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.control
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*TRAN 1e-008 1u 0
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run
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listing r
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display
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edisplay
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print q2b q3b q4b
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eprint hi clr clock q1 q2 q3 q4
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quit
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.endc
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.END
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